arch/powerpc/xmon/ppc-opc.c

2470

#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)

arch/powerpc/xmon/ppc-opc.c

2473

#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)

arch/powerpc/xmon/ppc-opc.c

4586

{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4587

{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4589

{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4590

{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4594

{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4595

{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4598

{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4599

{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4601

{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4602

{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4605

{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4606

{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4608

{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4609

{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

7104

{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},

arch/powerpc/xmon/ppc-opc.c

7105

{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},

drivers/atm/iphase.c

327

flot = NZ | (i << M_BITS) | (cr & M_MASK);

drivers/atm/iphase.c

329

flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK);

drivers/atm/iphase.c

331

flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK);

drivers/atm/iphase.c

346

mantissa = rate & M_MASK;

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

42

#define M(x) FIELD_PREP(M_MASK, ((x) - 2))

drivers/iommu/msm_iommu_hw-8xxx.h

1123

#define M (M_MASK << M_SHIFT)

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

117

regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val);

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

23

#define M(n) FIELD_PREP(M_MASK, (n))

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

39

#define CTRL_INIT_MASK (M_MASK | CCM_MASK | CA_MASK | TST_MASK | NB | RFB)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

1071

M_MASK, M(samsung->pll.fbdiv));

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

137

#define M(x) FIELD_PREP(M_MASK, x)