ATA_REG_LBAL
ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
IDECTRL_ADDR_LBAL = (ATA_REG_LBAL << 2) + 2,
ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping);
ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1;
ap->ioaddr.lbal_addr = base + ATA_REG_LBAL;
lbal = pi->proto->read_regr(pi, 0, ATA_REG_LBAL);
pi->proto->write_regr(pi, 0, ATA_REG_LBAL,
pi->proto->write_regr(pi, 0, ATA_REG_LBAL, tf->lbal);
tf->lbal = pi->proto->read_regr(pi, 0, ATA_REG_LBAL);
tf->hob_lbal = pi->proto->read_regr(pi, 0, ATA_REG_LBAL);
pi->proto->write_regr(pi, 0, ATA_REG_LBAL, 0xaa);
pi->proto->write_regr(pi, 0, ATA_REG_LBAL, 0x55);
pi->proto->write_regr(pi, 0, ATA_REG_LBAL, 0xaa);
lbal = pi->proto->read_regr(pi, 0, ATA_REG_LBAL);
ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift);
(ATA_REG_LBAL << pdata->reg_shift);
mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
buf[18] = (1 << 5) | ATA_REG_LBAL;
buf[i++] = (1 << 5) | ATA_REG_LBAL;
buf[i++] = (2 << 5) | ATA_REG_LBAL;
ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);