MSR_ME
msr |= MSR_ME;
#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_HV)
#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
#define MSR_ (MSR_ME | MSR_RI | MSR_CE)
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
{MSR_ME, "ME"},
__kvmppc_set_msr_hv(vcpu, MSR_ME);
vcpu->arch.intr_msr = MSR_SF | MSR_ME;
msr = (msr | MSR_ME) & ~MSR_HV;
vcpu->arch.shregs.msr = (vcpu->arch.regs.msr | MSR_ME) & ~MSR_HV;
WARN_ON_ONCE(!(vcpu->arch.shregs.msr & MSR_ME));
mtspr(SPRN_HSRR1, (vcpu->arch.shregs.msr & ~MSR_HV) | MSR_ME);
smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE;
msr = (msr & ~MSR_HV) | MSR_ME;
msr_mask = MSR_CE | MSR_ME | MSR_DE;
msr_mask = MSR_ME;
allowed = vcpu->arch.shared->msr & MSR_ME;
msr_mask = MSR_CE | MSR_ME | MSR_DE;
msr_mask = MSR_ME;
mask = ~(MSR_HV | MSR_S | MSR_ME);
op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
(MSR_LE|MSR_RI|MSR_DR|MSR_IR|MSR_ME|MSR_PR|