MSR_IA32_U_CET
wrmsrq(MSR_IA32_U_CET, 0);
wrmsrq(MSR_IA32_U_CET, CET_SHSTK_EN);
rdmsrq(MSR_IA32_U_CET, msrval);
wrmsrq(MSR_IA32_U_CET, msrval);
wrmsrq(MSR_IA32_U_CET, 0);
const u32 MSR_IA32_X_CET = cpl == 3 ? MSR_IA32_U_CET : MSR_IA32_S_CET;
if ((u_cet && ctxt->ops->get_msr(ctxt, MSR_IA32_U_CET, &u_cet)) ||
svm_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, !shstk_enabled);
MSR_IA32_U_CET, MSR_TYPE_RW);
vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, intercept);
if (__kvm_emulate_msr_read(vcpu, MSR_IA32_U_CET, &u_cet) ||
case MSR_IA32_U_CET:
case MSR_IA32_U_CET:
MSR_IA32_U_CET, MSR_IA32_S_CET,
case MSR_IA32_U_CET:
case MSR_IA32_U_CET:
case MSR_IA32_U_CET:
case MSR_IA32_U_CET:
if (msr->index != MSR_IA32_U_CET &&
MSR_TEST2(MSR_IA32_U_CET, CET_SHSTK_EN, CET_RESERVED, SHSTK, IBT),
MSR_TEST2(MSR_IA32_U_CET, CET_ENDBR_EN, CET_RESERVED, IBT, SHSTK),