MSR_IA32_APICBASE_ENABLE
l &= ~MSR_IA32_APICBASE_ENABLE;
if (l & MSR_IA32_APICBASE_ENABLE)
if (!(l & MSR_IA32_APICBASE_ENABLE)) {
l |= MSR_IA32_APICBASE_ENABLE | addr;
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
if (value & MSR_IA32_APICBASE_ENABLE) {
else if (value & MSR_IA32_APICBASE_ENABLE)
if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) {
if ((value & MSR_IA32_APICBASE_ENABLE) &&
msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
~(MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD));
rdmsr(MSR_IA32_APICBASE) | MSR_IA32_APICBASE_ENABLE);
} else if (!(val & MSR_IA32_APICBASE_ENABLE)) {
wrmsr(MSR_IA32_APICBASE, val | MSR_IA32_APICBASE_ENABLE);
MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD);
#define LAPIC_X2APIC (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)
TEST_ASSERT(apic_base & MSR_IA32_APICBASE_ENABLE,
vcpu_set_msr(vcpu, MSR_IA32_APICBASE, MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);