MSR_HV
msr &= ~MSR_HV;
#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_HV)
#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
if (!(msr & MSR_HV))
if (!(msr & MSR_HV))
if (msr & MSR_HV)
if (!(msr & MSR_HV))
if (!(msr & MSR_HV))
hv_mode = !!(mfmsr() & MSR_HV);
if (!(mfmsr() & MSR_HV)) {
if (mfmsr() & MSR_HV)
{MSR_HV, "HV"},
if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && (mfmsr() & MSR_HV))
if (!(regs->msr & MSR_HV))
if (kvmppc_get_msr(vcpu) & MSR_HV)
if (guest_msr & MSR_HV)
if (kvmppc_get_msr(vcpu) & MSR_HV)
(mfmsr() & MSR_HV))
if (!kvmhv_is_nestedv2() && (__kvmppc_get_msr_hv(vcpu) & MSR_HV)) {
if (__kvmppc_get_msr_hv(vcpu) & MSR_HV) {
msr = (msr | MSR_ME) & ~MSR_HV;
vcpu->arch.shregs.msr = (vcpu->arch.regs.msr | MSR_ME) & ~MSR_HV;
WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_HV);
mtspr(SPRN_HSRR1, (vcpu->arch.shregs.msr & ~MSR_HV) | MSR_ME);
smsr |= MSR_HV;
msr = (msr & ~MSR_HV) | MSR_ME;
if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) &&
mask = ~(MSR_HV | MSR_S | MSR_ME);
bool hvmode = !!(mfmsr() & MSR_HV);
#ifdef MSR_HV
if (mfmsr() & MSR_HV)
if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
MSR_ILE|MSR_HV|MSR_SF)) == (MSR_DR|MSR_SF)) {
if (!(mfmsr() & MSR_HV))
if (!(msr & MSR_HV))
bool hv = mfmsr() & MSR_HV;
if (mfmsr() & MSR_HV)
if (mfmsr() & MSR_HV)
is_hv = !!(uctx->uc_mcontext.gp_regs[PT_MSR] & MSR_HV);