arch/arm64/crypto/aes-glue.c

657

.cra_driver_name = "ecb-aes-" MODE,

arch/arm64/crypto/aes-glue.c

671

.cra_driver_name = "cbc-aes-" MODE,

arch/arm64/crypto/aes-glue.c

686

.cra_driver_name = "ctr-aes-" MODE,

arch/arm64/crypto/aes-glue.c

702

.cra_driver_name = "xctr-aes-" MODE,

arch/arm64/crypto/aes-glue.c

718

.cra_driver_name = "xts-aes-" MODE,

arch/arm64/crypto/aes-glue.c

735

.cra_driver_name = "cts-cbc-aes-" MODE,

arch/arm64/crypto/aes-glue.c

751

.cra_driver_name = "essiv-cbc-aes-sha256-" MODE,

arch/arm64/crypto/aes-glue.c

898

.base.cra_driver_name = "cmac-aes-" MODE,

arch/arm64/crypto/aes-glue.c

915

.base.cra_driver_name = "xcbc-aes-" MODE,

arch/arm64/crypto/aes-glue.c

932

.base.cra_driver_name = "cbcmac-aes-" MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

142

MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

480

MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

873

MODE, is_mode_set ? wave_launch_mode : 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

911

MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

925

MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

759

MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

334

MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

337

MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

807

MODE, is_mode_set ? wave_launch_mode : 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

841

MODE,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3999

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6379

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5946

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3043

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

103

MODE, DP2_LINK_TRAINING_TPS1);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

107

MODE, DP2_LINK_TRAINING_TPS2);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

116

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

125

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

139

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

153

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

167

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

181

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

195

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

209

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

242

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

258

MODE, DP2_TEST_PATTERN);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

465

MODE, (uint32_t *)&state->link_mode);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

99

MODE, DP2_LINK_ACTIVE);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

115

SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

146

type MODE;\

drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h

36

SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\

drivers/gpu/drm/mediatek/mtk_dsi.c

1132

if (dsi_mode & MODE) {

drivers/gpu/drm/mediatek/mtk_dsi.c

1182

if (dsi_mode & MODE) {

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

145

MODE(21000, 512, 384, 840, 500, N, N, 181.797557582, 5_4, 0x6, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

146

MODE(26250, 512, 384, 840, 625, N, N, 145.438046066, 1_1, 0x1, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

147

MODE(20140, 512, 384, 800, 420, N, N, 213.257083791, 5_4, 0x4, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

148

MODE(24671, 512, 384, 784, 525, N, N, 174.0874153, 1_1, 0x3, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

149

MODE(28125, 720, 400, 1125, 500, N, N, 135.742176298, 5_4, 0x6, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

150

MODE(34875, 720, 400, 1116, 625, N, N, 109.469496898, 1_1, 0x1, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

151

MODE(23790, 720, 400, 945, 420, N, N, 160.475642016, 5_4, 0x4, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

152

MODE(29455, 720, 400, 936, 525, N, N, 129.614941843, 1_1, 0x3, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

153

MODE(25000, 640, 400, 1000, 500, N, N, 152.709948279, 5_4, 0x6, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

154

MODE(31500, 640, 400, 1008, 625, N, N, 121.198371646, 1_1, 0x1, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

155

MODE(21147, 640, 400, 840, 420, N, N, 180.535097338, 5_4, 0x4, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

156

MODE(26434, 640, 400, 840, 525, N, N, 144.42807787, 1_1, 0x2, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

157

MODE(30210, 640, 400, 840, 600, N, N, 126.374568276, 7_8, 0x1, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

158

MODE(21000, 640, 480, 840, 500, N, N, 181.797557582, 5_4, 0x4, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

159

MODE(26250, 640, 480, 840, 625, N, N, 145.438046066, 1_1, 0x2, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

160

MODE(31500, 640, 480, 840, 750, N, N, 121.198371646, 5_6, 0x1, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

161

MODE(24671, 640, 480, 784, 525, N, N, 174.0874153, 1_1, 0x4, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

162

MODE(28196, 640, 480, 784, 600, N, N, 152.326488422, 7_8, 0x2, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

163

MODE(30210, 640, 480, 800, 630, N, N, 142.171389101, 5_6, 0x1, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

165

MODE(36000, 800, 600, 960, 750, P, P, 119.304647022, 5_6, 0x6, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

166

MODE(39000, 800, 600, 936, 836, P, P, 110.127366499, 3_4, 0x1, PAL_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

167

MODE(39273, 800, 600, 1040, 630, P, P, 145.816809399, 5_6, 0x4, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

168

MODE(43636, 800, 600, 1040, 700, P, P, 131.235128487, 3_4, 0x2, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

169

MODE(47832, 800, 600, 1064, 750, P, P, 119.723275165, 7_10, 0x1, NTSC_LIKE),

drivers/gpu/drm/nouveau/dispnv50/base507c.c

181

NVVAL(NV507C, SET_NOTIFIER_CONTROL, MODE, asyw->ntfy.awaken) |

drivers/gpu/drm/nouveau/dispnv50/base907c.c

95

NVVAL(NV907C, SET_BASE_LUT_LO, MODE, asyw->xlut.i.mode),

drivers/gpu/drm/nouveau/dispnv50/core507d.c

44

NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

91

NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

62

NVDEF(NVC37D, SET_NOTIFIER_CONTROL, MODE, WRITE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

37

NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, MODE, WRITE) |

drivers/gpu/drm/nouveau/dispnv50/head.c

122

asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);

drivers/gpu/drm/nouveau/dispnv50/head507d.c

305

NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

358

NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, MODE, CLK_CUSTOM) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

61

NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

139

NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

275

NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

368

NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

90

NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

drivers/gpu/drm/nouveau/dispnv50/head917d.c

43

NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

146

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND));

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

99

NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

123

NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

104

NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

164

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

209

NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) |

drivers/gpu/drm/nouveau/dispnv50/ovly507e.c

71

NVDEF(NV507E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE));

drivers/gpu/drm/nouveau/dispnv50/ovly827e.c

48

NVDEF(NV827E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE));

drivers/gpu/drm/nouveau/dispnv50/ovly907e.c

45

NVDEF(NV907E, SET_COMPOSITION_CONTROL, MODE, OPAQUE));

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

235

NVVAL(NVC37E, SET_NOTIFIER_CONTROL, MODE, asyw->ntfy.awaken) |

drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c

136

NVVAL(NVC57E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) |

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

133

NVVAL(NVCA7E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) |

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

177

NVVAL(NVCA7E, SET_NOTIFIER_CONTROL, MODE, asyw->ntfy.awaken));

drivers/gpu/drm/nouveau/nouveau_connector.h

75

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, DYNAMIC_2X2),

drivers/gpu/drm/nouveau/nouveau_connector.h

77

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, STATIC_2X2),

drivers/gpu/drm/nouveau/nouveau_connector.h

79

NVDEF(NV907D, HEAD_SET_DITHER_CONTROL, MODE, TEMPORAL),

drivers/media/dvb-frontends/bcm3510.c

506

cmd.ACQUIRE0.MODE = 0x1;

drivers/media/dvb-frontends/bcm3510.c

511

cmd.ACQUIRE0.MODE = 0x2;

drivers/media/dvb-frontends/bcm3510.c

517

cmd.ACQUIRE0.MODE = 0x3;

drivers/media/dvb-frontends/bcm3510.c

520

cmd.ACQUIRE0.MODE = 0x4;

drivers/media/dvb-frontends/bcm3510.c

523

cmd.ACQUIRE0.MODE = 0x5;

drivers/media/dvb-frontends/bcm3510.c

526

cmd.ACQUIRE0.MODE = 0x6;

drivers/media/dvb-frontends/bcm3510.c

529

cmd.ACQUIRE0.MODE = 0x7;

drivers/media/dvb-frontends/bcm3510.c

533

cmd.ACQUIRE0.MODE = 0x8;

drivers/media/dvb-frontends/bcm3510.c

538

cmd.ACQUIRE0.MODE = 0x9;

drivers/media/dvb-frontends/bcm3510_priv.h

176

u8 MODE :4;

drivers/media/dvb-frontends/bcm3510_priv.h

201

u8 MODE :4;

drivers/media/i2c/tc358746.c

738

MODE(MODE_SET) |

drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h

40

u32 MODE;

drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c

1017

iowrite32(mode, &hw->reg->MODE);

drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c

349

iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);

drivers/phy/tegra/xusb-tegra186.c

146

#define MODE_HS MODE(0)

drivers/phy/tegra/xusb-tegra186.c

147

#define MODE_RST MODE(1)

drivers/pinctrl/bcm/pinctrl-bcm281xx.c

1975

BCM281XX_PIN_SHIFT(HDMI, MODE),

drivers/pinctrl/bcm/pinctrl-bcm281xx.c

1976

BCM281XX_PIN_MASK(HDMI, MODE));

drivers/pinctrl/pinctrl-tb10x.c

400

#define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \

drivers/pinctrl/pinctrl-tb10x.c

403

.port = (PORT), .mode = (MODE), \

drivers/power/supply/max77976_charger.c

430

err = regmap_field_write(chg->rfield[MODE], MAX77976_MODE_CHARGER_BUCK);

drivers/power/supply/max77976_charger.c

98

[MODE] = REG_FIELD(MAX77976_REG_CHG_CNFG_00, 0, 3),

drivers/soc/bcm/brcmstb/pm/pm-mips.c

103

ctx->cp0_regs[MODE] = read_c0_brcm_mode();

drivers/soc/bcm/brcmstb/pm/pm-mips.c

126

write_c0_brcm_mode(ctx->cp0_regs[MODE]);

fs/proc/base.c

163

#define NOD(NAME, MODE, IOP, FOP, OP) { \

fs/proc/base.c

166

.mode = MODE, \

fs/proc/base.c

172

#define DIR(NAME, MODE, iops, fops) \

fs/proc/base.c

173

NOD(NAME, (S_IFDIR|(MODE)), &iops, &fops, {} )

fs/proc/base.c

178

#define REG(NAME, MODE, fops) \

fs/proc/base.c

179

NOD(NAME, (S_IFREG|(MODE)), NULL, &fops, {})

fs/proc/base.c

180

#define ONE(NAME, MODE, show) \

fs/proc/base.c

181

NOD(NAME, (S_IFREG|(MODE)), \

fs/proc/base.c

184

#define ATTR(LSMID, NAME, MODE) \

fs/proc/base.c

185

NOD(NAME, (S_IFREG|(MODE)), \

sound/soc/codecs/ak4613.c

486

mode = AK4613_CONFIG_GET(priv, MODE);

sound/soc/codecs/ak4613.c

619

tdm = AK4613_CONFIG_GET(priv, MODE);