MIPI_DCS_SET_ADDRESS_MODE
mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x48);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, cfg->address_mode);
ILI9805_INSTR(0, MIPI_DCS_SET_ADDRESS_MODE, 0x0a),
ILI9805_INSTR(0, MIPI_DCS_SET_ADDRESS_MODE, 0x08),
ili9881c_send_cmd_data(&mctx, MIPI_DCS_SET_ADDRESS_MODE,
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x02);
ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &conf->madctl,
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, 0x0a);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, 0x0a);
mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x04);
mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
MIPI_DCS_SET_ADDRESS_MODE, 0x40);
ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x17);
ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x10);
ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0);
MIPI_DCS_SET_ADDRESS_MODE));
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, 0x01);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, par->bgr << 3);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0xC0);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0xC0);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, val);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, mactrl_data);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, val | (par->bgr << 3));
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
-1, MIPI_DCS_SET_ADDRESS_MODE, 0x08,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, madctl_par);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x58);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x28);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x58);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x38);
write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x08);