MII_CTRL1000
case MII_CTRL1000:
et131x_mii_read(adapter, MII_CTRL1000, &tmp);
val = MII_CTRL1000 << 16 | ADVERTISE_1000FULL;
alx_write_phy_reg(hw, MII_CTRL1000, giga) ||
atl1c_write_phy_reg(hw, MII_CTRL1000, mii_giga_ctrl_data) != 0)
ret_val = atl1e_write_phy_reg(hw, MII_CTRL1000,
err = atl1e_write_phy_reg(hw, MII_CTRL1000,
if ((atl1e_write_phy_reg(hw, MII_CTRL1000, 0) != 0) ||
port->phy_id, MII_CTRL1000);
bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
(reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
if (!tg3_readphy(tp, MII_CTRL1000, ®))
if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
tg3_writephy(tp, MII_CTRL1000,
tg3_writephy(tp, MII_CTRL1000, phy9_orig);
err = tg3_writephy(tp, MII_CTRL1000, new_adv);
err = tg3_readphy(tp, MII_CTRL1000, &val);
if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
tg3_readphy(tp, MII_CTRL1000, &val);
tg3_writephy(tp, MII_CTRL1000, val);
err = t3_mdio_read(phy, MDIO_DEVAD_NONE, MII_CTRL1000, &val);
err = t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_CTRL1000, val);
mscr = mii_read (dev, phy_addr, MII_CTRL1000);
mscr = mii_read (dev, phy_addr, MII_CTRL1000);
mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
adv = phy_read(phy, MII_CTRL1000);
phy_write(phy, MII_CTRL1000, adv);
int adv = phy_read(phy, MII_CTRL1000);
ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
case MII_CTRL1000:
ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
return e1e_wphy(hw, MII_CTRL1000, phy_data);
ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
ret_val = e1e_wphy(hw, MII_CTRL1000, data);
ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
MII_CTRL1000,
ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
MII_CTRL1000, MII_READ);
if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
gigadv = mdio_read(ioaddr, phy_id, MII_CTRL1000);
err = mii_read(np, np->phy_addr, MII_CTRL1000);
err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
MII_CTRL1000, ctrl1000);
MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs))
else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
velocity_mii_read(vptr->mac_regs, MII_CTRL1000, &CTRL1000);
velocity_mii_write(vptr->mac_regs, MII_CTRL1000, CTRL1000);
ctrl1000 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
mii->mdio_write(dev, mii->phy_id, MII_CTRL1000, tmp2);
MII_CTRL1000);
mii->mdio_write(dev, mii->phy_id, MII_CTRL1000, tmp2);
ctrl1000 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
AS21XXX_MDIO_AN_C22 + MII_CTRL1000);
phy_write(phydev, MII_CTRL1000, 0);
MDIO_AN_C22 + MII_CTRL1000,
val = phy_read(phydev, MII_CTRL1000);
phy_write(phydev, MII_CTRL1000, val);
ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
reg = phy_read(phydev, MII_CTRL1000);
err = phy_write(phydev, MII_CTRL1000, reg);
ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv);
result = phy_read(phydev, MII_CTRL1000);
result = phy_write(phydev, MII_CTRL1000, result);
ret = phy_read(phydev, MII_CTRL1000);
return phy_write(phydev, MII_CTRL1000, ret);
rv = phy_modify(phydev, MII_CTRL1000,
ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
int adv = __phy_read(phydev, MII_CTRL1000);
return __phy_modify_changed(phydev, MII_CTRL1000,
err = __phy_modify_changed(phydev, MII_CTRL1000,
ret = phy_modify_changed(phydev, MII_CTRL1000,
case MII_CTRL1000:
err = phy_modify_changed(phydev, MII_CTRL1000,
return phy_modify_changed(phydev, MII_CTRL1000,
val = phy_read(phydev, MII_CTRL1000);
int adv = phy_read(phydev, MII_CTRL1000);
context->control1000 = phy_read(phydev, MII_CTRL1000);
phy_write(phydev, MII_CTRL1000, context->control1000);
phy_write(phydev, MII_CTRL1000, 0);
phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
RTL822X_VND2_C22_REG(MII_CTRL1000),
ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
ret = phy_read(phydev, MII_CTRL1000);
return phy_set_bits(phydev, MII_CTRL1000,
asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
orig = r8152_mdio_read(tp, MII_CTRL1000);
r8152_mdio_write(tp, MII_CTRL1000, new1);
smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,