drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

231

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

237

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

33

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

37

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

41

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

45

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

49

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

53

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h

34

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h

38

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h

42

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h

46

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

246

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

252

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

258

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

264

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

34

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

38

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

42

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

46

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

50

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

54

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

268

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

274

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

280

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

286

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

32

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

36

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

40

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

44

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

48

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

52

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

56

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 14),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

60

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 15),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h

29

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h

33

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h

37

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h

41

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

244

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

250

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

256

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

262

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

32

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

36

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

40

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

44

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

48

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

52

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

43

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

48

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

52

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

56

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

60

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

235

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

241

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

43

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

47

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

51

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

55

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

59

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

63

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

235

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

241

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

43

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

47

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

51

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

55

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

59

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

63

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

40

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

44

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

48

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

52

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

56

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

60

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

37

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

41

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

45

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

49

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

53

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

57

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

37

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

41

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

45

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

49

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

53

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

57

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

234

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

240

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

42

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

46

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

50

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

54

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

58

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

62

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h

35

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h

39

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h

43

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h

32

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h

38

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h

42

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h

46

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h

50

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h

32

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h

33

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

234

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

240

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

42

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

46

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

50

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

54

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

58

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

62

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

36

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

40

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

44

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

48

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

233

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

239

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

41

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

45

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

49

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

53

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

57

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

61

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

234

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

240

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

42

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

46

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

50

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

54

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

58

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

62

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

233

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

239

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

41

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

45

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

49

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

53

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

57

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

61

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

230

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

236

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

33

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

37

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

41

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

45

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

49

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

53

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

230

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

236

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

33

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

37

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

41

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

45

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

49

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

53

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

230

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

236

.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

32

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

36

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

40

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

44

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

48

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

52

.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

144

[MDP_SSPP_TOP0_INTR2] = {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

220

[MDP_SSPP_TOP0_INTR2] = {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

605

BIT(MDP_SSPP_TOP0_INTR2) |

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

73

[MDP_SSPP_TOP0_INTR2] = {