drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
207
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
213
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
219
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
225
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
327
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
357
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
358
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
365
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
366
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
374
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
375
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
383
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
384
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
222
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
228
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
234
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
240
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
369
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
399
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
400
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
407
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
408
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
416
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
417
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
425
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
426
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
244
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
250
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
256
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
262
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
376
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
406
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
407
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
414
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
415
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
423
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
424
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
432
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
433
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
440
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
441
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
448
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
449
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
456
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
457
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
464
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
465
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
472
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
473
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
220
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
226
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
232
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
238
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
367
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
397
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
398
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
405
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
406
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
414
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
415
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
423
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
424
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
103
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
104
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
109
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
110
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
129
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
130
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
137
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
138
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
116
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
117
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
96
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
97
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
103
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
104
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
109
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
110
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
128
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
129
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
136
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
137
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
144
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
145
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
184
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
185
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
190
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
191
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
196
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
197
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
202
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
203
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
235
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
236
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
243
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
244
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
251
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
252
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
258
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
259
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
168
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
169
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
174
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
175
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
180
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
181
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
186
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
187
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
220
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
221
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
228
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
229
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
236
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
237
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
243
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
244
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
139
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
140
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
145
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
146
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
151
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
152
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
157
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
158
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
191
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
192
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
199
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
200
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
207
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
208
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
113
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
114
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
119
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
120
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
139
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
140
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
147
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
148
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
193
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
194
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
199
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
200
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
205
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
206
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
211
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
212
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
239
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
240
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
247
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
248
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
255
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
256
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
263
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
264
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
211
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
217
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
223
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
229
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
285
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
296
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
297
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
304
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
305
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
313
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
314
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
322
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
323
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
211
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
217
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
223
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
229
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
291
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
302
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
303
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
310
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
311
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
319
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
320
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
330
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
331
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
338
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
339
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
346
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
347
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
160
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
166
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
172
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
178
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
209
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
210
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
217
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
218
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
226
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
227
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
235
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
236
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
251
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
138
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
143
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
148
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
163
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
174
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
175
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
182
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
183
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
191
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
192
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
121
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
127
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
142
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
153
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
154
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
161
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
162
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
210
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
216
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
222
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
228
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
280
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
281
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
288
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
289
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
297
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
298
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
306
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
307
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
322
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
116
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
122
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
133
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
134
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
141
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
142
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
158
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
80
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
91
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
92
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
124
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
130
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
152
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
163
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
164
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
171
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
172
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
80
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
91
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
92
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
100
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
101
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
82
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
210
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
216
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
222
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
228
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
295
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
306
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
307
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
314
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
315
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
323
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
324
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
332
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
333
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
127
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
133
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
139
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
145
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
177
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
188
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
189
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
196
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
197
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
205
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
206
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
209
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
215
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
221
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
227
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
299
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
300
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
307
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
308
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
316
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
317
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
325
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
326
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
333
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
334
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
341
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
342
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
349
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
350
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
357
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
358
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
365
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
366
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
210
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
216
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
222
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
228
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
308
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
319
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
320
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
327
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
328
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
336
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
337
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
345
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
346
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
209
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
215
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
221
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
227
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
315
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
327
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
328
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
335
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
336
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
344
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
345
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
353
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
354
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
361
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
362
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
369
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
370
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
377
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
378
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
385
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
386
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
206
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
212
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
218
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
224
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
303
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
314
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
315
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
322
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
323
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
331
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
332
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
340
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
341
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
206
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
212
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
218
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
224
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
303
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
314
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
315
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
322
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
323
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
331
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
332
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
340
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
341
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
206
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
212
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
218
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
224
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
303
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
315
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
316
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
323
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
324
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
332
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
333
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
341
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
342
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
349
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
350
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
357
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
358
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
365
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
366
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
373
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
374
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
381
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
382
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
139
[MDP_SSPP_TOP0_INTR] = {
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
215
[MDP_SSPP_TOP0_INTR] = {
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
604
intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) |
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
68
[MDP_SSPP_TOP0_INTR] = {
