drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10326

struct dc_surface_update surface_updates[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10327

struct dc_plane_info plane_infos[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10328

struct dc_scaling_info scaling_infos[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10329

struct dc_flip_addrs flip_addrs[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11579

dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3658

struct dc_surface_update surface_updates[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3659

struct dc_plane_info plane_infos[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3660

struct dc_scaling_info scaling_infos[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3661

struct dc_flip_addrs flip_addrs[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/core/dc.c

3731

struct dc_plane_state *new_planes[MAX_SURFACES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

5439

struct dc_surface_update srf_updates[MAX_SURFACES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

5849

struct dc_fast_update fast_update[MAX_SURFACES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

5935

struct dc_fast_update fast_update[MAX_SURFACES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

7930

struct dc_surface_update intermediate_updates[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/core/dc.c

8008

struct dc_fast_update fast_update[MAX_SURFACES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_state.c

517

} else if (stream_status->plane_count == MAX_SURFACES) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

519

plane_state, MAX_SURFACES);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

634

struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_state.c

914

struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };

drivers/gpu/drm/amd/display/dc/dc.h

1658

struct dc_plane_state plane_states[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/dc.h

2063

struct dc_plane_state *plane_states[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/dc_stream.h

61

struct dc_plane_state *plane_states[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

845

struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };