MAX_PIPES - Linux

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10644

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12495

struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3086

struct dc_stream_state *del_streams[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1300

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1576

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1678

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1762

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1862

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1946

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2046

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2126

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2223

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2301

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2355

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2424

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2493

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1250

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1101

bool tried[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1102

int kbps_increase[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1194

struct dsc_mst_fairness_params params[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1357

struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1373

for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1488

bool computed_streams[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1558

bool computed_streams[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

998

bool bpp_increased[MAX_PIPES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

999

int initial_slack[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3012

const struct pipe_ctx *active_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

170

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

140

for (k = 0; k < MAX_PIPES; k++)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

514

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

517

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

564

uint32_t pix_clk_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

565

int p_state_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

566

int disp_src_width_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

567

int disp_src_height_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

568

uint64_t disp_src_refresh_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

569

bool is_scaled_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

284

bool dppclk_active[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

330

for (i = 0; i < MAX_PIPES * 2; ++i) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

418

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

421

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

466

uint32_t pix_clk_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

467

int p_state_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

468

int disp_src_width_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

469

int disp_src_height_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

470

uint64_t disp_src_refresh_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

471

bool is_scaled_list[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

1315

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1607

struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/core/dc.c

1633

struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/core/dc.c

1647

struct pipe_ctx *pipe_set[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

2027

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2283

for (k = 0; k < MAX_PIPES; k++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2534

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2664

for (j = 0; j < MAX_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3458

char force_odm[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

431

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

495

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

537

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5694

enum mall_stream_type subvp_pipe_type[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

603

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6064

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

610

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc.c

6345

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6352

if (i == MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6396

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6403

if (i == MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6573

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6621

for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

669

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

676

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc.c

6767

for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6808

for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6835

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6852

for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6880

for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6948

for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7066

for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

794

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

800

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc.c

820

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

842

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

883

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

902

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

925

struct pipe_ctx *pipes_affected[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

933

for (j = 0; j < MAX_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1630

struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1635

memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2095

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2112

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2132

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

101

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

237

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

253

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

303

for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

399

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

405

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

418

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

469

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

508

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

532

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

582

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

604

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

630

int eng_ids_per_ep_id[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

631

int ep_ids_per_eng_id[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

635

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

648

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

658

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

666

for (j = 0; j < MAX_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

691

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

735

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

107

if (current_snapshot->line_count >= MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1454

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1746

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2000

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2010

struct pipe_ctx *opp_heads[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2026

ASSERT(i < MAX_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2035

struct pipe_ctx *dpp_pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2045

ASSERT(i < MAX_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2054

struct pipe_ctx *dpp_pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2059

for (j = 0; j < MAX_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2068

if (j < MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2267

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2422

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2423

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3073

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3479

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4175

struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4176

struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4177

struct dc_stream_state *add_streams[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5679

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5680

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

737

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

151

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

266

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

413

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

715

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

745

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

783

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

810

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

816

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

840

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

846

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

882

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dc.h

1183

uint32_t dml21_force_pstate_method_values[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1200

uint32_t acpi_transition_bitmasks[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1821

bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */

drivers/gpu/drm/amd/display/dc/dc.h

1882

struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1883

struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1884

struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1885

struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1886

struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1887

struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

1888

struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

2957

} hubp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

2997

} dpp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

3006

uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */

drivers/gpu/drm/amd/display/dc/dc.h

3007

uint32_t dppclk_enable[MAX_PIPES];       /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */

drivers/gpu/drm/amd/display/dc/dc.h

3008

uint32_t dppclk_dto_enable[MAX_PIPES];   /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */

drivers/gpu/drm/amd/display/dc/dc.h

3009

uint32_t dppclk_dto_phase[MAX_PIPES];    /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */

drivers/gpu/drm/amd/display/dc/dc.h

3010

uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */

drivers/gpu/drm/amd/display/dc/dc.h

3013

uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */

drivers/gpu/drm/amd/display/dc/dc.h

3014

uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */

drivers/gpu/drm/amd/display/dc/dc.h

3015

uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */

drivers/gpu/drm/amd/display/dc/dc.h

3016

uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */

drivers/gpu/drm/amd/display/dc/dc.h

3019

uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */

drivers/gpu/drm/amd/display/dc/dc.h

3020

uint32_t otg_pixel_rate_div[MAX_PIPES];  /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */

drivers/gpu/drm/amd/display/dc/dc.h

3021

uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */

drivers/gpu/drm/amd/display/dc/dc.h

3022

uint32_t pipe_dto_src_sel[MAX_PIPES];    /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */

drivers/gpu/drm/amd/display/dc/dc.h

3023

uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */

drivers/gpu/drm/amd/display/dc/dc.h

3024

uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */

drivers/gpu/drm/amd/display/dc/dc.h

3025

uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */

drivers/gpu/drm/amd/display/dc/dc.h

3033

uint32_t dpstreamclk_enable[MAX_PIPES];          /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */

drivers/gpu/drm/amd/display/dc/dc.h

3089

} dsc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

3094

uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */

drivers/gpu/drm/amd/display/dc/dc.h

3095

uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */

drivers/gpu/drm/amd/display/dc/dc.h

3096

uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */

drivers/gpu/drm/amd/display/dc/dc.h

3097

uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */

drivers/gpu/drm/amd/display/dc/dc.h

3098

uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */

drivers/gpu/drm/amd/display/dc/dc.h

3099

uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */

drivers/gpu/drm/amd/display/dc/dc.h

3100

uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */

drivers/gpu/drm/amd/display/dc/dc.h

3101

uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */

drivers/gpu/drm/amd/display/dc/dc.h

3104

uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */

drivers/gpu/drm/amd/display/dc/dc.h

3105

uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */

drivers/gpu/drm/amd/display/dc/dc.h

3108

uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */

drivers/gpu/drm/amd/display/dc/dc.h

3109

uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */

drivers/gpu/drm/amd/display/dc/dc.h

3110

uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */

drivers/gpu/drm/amd/display/dc/dc.h

3113

uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */

drivers/gpu/drm/amd/display/dc/dc.h

3114

uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */

drivers/gpu/drm/amd/display/dc/dc.h

3115

uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */

drivers/gpu/drm/amd/display/dc/dc.h

3167

} opp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

3316

} optc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

869

bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

420

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

138

type OTG_ADD_PIXEL[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

139

type OTG_DROP_PIXEL[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

175

type DTBCLK_DTO_ENABLE[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

176

type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

177

type PIPE_DTO_SRC_SEL[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

178

type DTBCLK_DTO_DIV[MAX_PIPES];\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

367

type DP_DTO_ENABLE[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

394

uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

401

uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

402

uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

434

uint32_t DP_DTO_MODULO[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

435

uint32_t DP_DTO_PHASE[MAX_PIPES]; \

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

189

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

510

for (k = 0; k < MAX_PIPES; k++)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

228

uint32_t PHASE[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

229

uint32_t MODULO[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

230

uint32_t PIXEL_RATE_CNTL[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

305

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

128

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

709

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2036

int pipe_split_from[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2327

int pipe_split_from[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1173

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1203

int split[MAX_PIPES],

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1204

bool merge[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1286

struct vba_vars_st *vba, int split[MAX_PIPES],

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1287

bool merge[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1404

unsigned int cur_policy[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1414

memset(split, 0, MAX_PIPES * sizeof(int));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1415

memset(merge, 0, MAX_PIPES * sizeof(bool));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1477

memset(split, 0, MAX_PIPES * sizeof(int));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1478

memset(merge, 0, MAX_PIPES * sizeof(bool));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1945

bool newly_split[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2147

int split[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2148

bool merge[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

476

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

492

ASSERT(i < MAX_PIPES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

47

for (int i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

349

unsigned int preferred_pipe_candidates[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

350

unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

415

unsigned int preferred_pipe_candidates[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

416

unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

47

unsigned int odm_slice_end_x[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

48

struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

612

unsigned int pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

650

unsigned int pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

911

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

927

struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

943

struct dml2_pipe_combine_factor odm_factors[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

960

struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

989

struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

131

struct dml2_pipe_combine_factor odm_factors[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

132

struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES][MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1002

ASSERT(i < MAX_PIPES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1281

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1320

for (k = 0; k < MAX_PIPES; k++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

989

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

519

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

100

struct pipe_ctx *opp_heads[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

103

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

236

enum dml2_force_pstate_methods force_pstate_method_values[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1081

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2048

for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2089

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2290

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3303

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1430

TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1576

bool tg_enabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1710

if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2390

uint64_t phase[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2391

uint64_t modulo[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2402

hw_crtc_timing = kzalloc_objs(*hw_crtc_timing, MAX_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3573

for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1180

int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3179

for (j = 0; j < MAX_PIPES; j++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

826

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

836

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

303

for (j = 0; j < MAX_PIPES; j++)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1248

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

177

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

403

bool otg_disabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

435

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

488

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1143

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1255

bool otg_disabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1287

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1386

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1737

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

433

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

628

bool tg_enabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

762

if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1035

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1544

struct pipe_ctx *old_opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1580

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1581

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1627

struct pipe_ctx *old_opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1717

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1718

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1818

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1819

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1913

struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3881

for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

732

struct pipe_ctx *opp_heads[MAX_PIPES],

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

775

int opp_inst[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

776

struct pipe_ctx *opp_heads[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1662

struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

198

int opp_inst[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

991

#define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES)

drivers/gpu/drm/amd/display/dc/inc/core_types.h

245

struct mem_input *mis[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

246

struct hubp *hubps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

247

struct input_pixel_processor *ipps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

248

struct transform *transforms[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

249

struct dpp *dpps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

250

struct output_pixel_processor *opps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

251

struct timing_generator *timing_generators[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

252

struct stream_encoder *stream_enc[MAX_PIPES * 2];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

257

struct dce_aux *engines[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

258

struct dce_i2c_hw *hw_i2cs[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

259

struct dce_i2c_sw *sw_i2cs[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

270

struct display_stream_compressor *dscs[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

291

struct dc_3dlut *mpc_lut[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

292

struct dc_transfer_func *mpc_shaper[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

325

struct abm *multiple_abms[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

518

struct link_enc_assignment link_enc_assignments[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

520

struct link_enc_assignment transient_assignments[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

524

struct pipe_ctx pipe_ctx[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

525

bool is_stream_enc_acquired[MAX_PIPES * 2];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

526

bool is_audio_acquired[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

529

bool is_dsc_acquired[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

536

bool is_mpc_3dlut_acquired[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

547

struct dce_watermarks urgent_wm_ns[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

548

struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

549

struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

550

struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

606

struct dc_stream_state *streams[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

611

struct dc_stream_status stream_status[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

196

int pipe_dppclk_khz[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

198

bool dpp_clock_gated[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

46

#define MAX_PHANTOM_PIPES (MAX_PIPES / 2)

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

96

struct pipe_topology_line pipe_log_lines[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

231

int dpp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

232

int mpcc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

240

bool mpcc_disconnect_pending[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

35

bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/resource.h

391

struct pipe_ctx *opp_heads[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

401

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

410

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

216

if (pipe_offset >= MAX_PIPES)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

146

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

666

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

69

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

78

struct audio_output audio_output[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

79

struct dc_stream_state *streams_on_link[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

973

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

984

if (i == MAX_PIPES)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

152

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

153

struct dc_stream_state *streams[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

210

struct pipe_ctx *pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

216

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

42

struct pipe_ctx *pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/link/link_resource.c

40

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

376

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

399

for (uint8_t i = 0; (i < MAX_PIPES && i < new_ctx->stream_count); i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

310

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

127

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

218

for (unsigned int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

285

for (unsigned int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

59

for (int i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1031

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1195

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

537

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

799

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

59

bool first_preferred_memory_for_opp[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

60

bool second_preferred_memory_for_opp[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

83

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

94

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

141

if (dsc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

232

if (hubp_dpp_inst < MAX_PIPES) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

353

if (mpcc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

363

if (opp_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

373

if (optc_inst < MAX_PIPES)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

561

memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1452

for (i = 0; i < MAX_PIPES; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2049

int split[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2050

bool merge[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2076

for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

804

int split[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

805

bool merge[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

869

for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1668

int split[MAX_PIPES] = { 0 };

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1669

bool merge[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1670

bool newly_split[MAX_PIPES] = { false };

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

316

uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

317

uint8_t pipe_counted[MAX_PIPES] = {0};

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

133

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

161

[MAX_PIPES] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

177

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

154

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

155

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

160

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

13

[MAX_PIPES] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

13

[MAX_PIPES] = GENMASK(7, 0),