IntLatch
outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
outw(SetIntrEnb | IntLatch|TxAvailable|TxComplete|RxComplete|StatsFull,
(IntLatch | RxComplete | StatsFull)) {
outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); /* Ack IRQ */
outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
} while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
(IntLatch | RxComplete | RxEarly | StatsFull)) {
outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
if ((inw(ioaddr + EL3_STATUS) & IntLatch) && (inb(ioaddr + Timer) == 0xff)) {
outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
(IntLatch | RxComplete | StatsFull)) {
outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
if ((inw(ioaddr + EL3_STATUS) & IntLatch) &&
vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
if ((status & IntLatch) == 0)
} while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
} while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
if ((status & IntLatch) == 0)
} while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
} while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);