A1
STS_BIT(regs, A2), STS_BIT(regs, A1),
.set USER_DA,LV+0 | save space for D0-D1,A0-A1
.set USER_A1,LV+12 | saved user A1
* Start ADC: run A1
int A1[3];
rq[A1] = create_rewinder(ce, NULL, slot, X);
if (IS_ERR(rq[A1])) {
rq[B1] = create_rewinder(ce, rq[A1], slot, Z);
GEM_BUG_ON(!i915_request_is_active(rq[A1]));
[0x1] = { COMMON_STEP(A1) },
[0x1] = { COMMON_STEP(A1) },
func(A1) \
SUBPLATFORM_CASE(DG2, G12, A1),
GMDID_CASE(BATTLEMAGE, 2001, A0, 1301, A1),
[0x1] = { COMMON_STEP(A1) },
[0x1] = { COMMON_STEP(A1) },
func(A1) \
u16 A1, u16 A2, u16 A3, u16 A4,
adv7511_wr_and_or(sd, 0x18, 0xe0, A1>>8);
adv7511_wr(sd, 0x19, A1);
sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
sdp_io_write(sd, 0xe1, c->A1);
IWL_MLD_ENC_EHT_RU(1_1_1, A1);
IWL_MVM_ENC_EHT_RU(1_1_1, A1);
ASPEED_PINCTRL_PIN(A1),
SIG_EXPR_LIST_DECL_SINGLE(A1, SD1WP, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A1, SDA13, I2C13, I2C13_DESC);
PIN_DECL_2(A1, GPIOC7, SD1WP, SDA13);
FUNC_GROUP_DECL(I2C13, B2, A1);
FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
PINMUX_IPSR_GPSR(IP4_11_8, A1),
PINMUX_SINGLE(A1),
PINMUX_IPSR_GPSR(IP1_29_28, A1),
PINMUX_IPSR_GPSR(IP0_20_19, A1),
PINMUX_SINGLE(A1),
PINMUX_IPSR_GPSR(IP1_24, A1),
#define GPSR1_1 F_(A1, IP2_3_0)
#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2_3_0, A1),
#define GPSR1_1 F_(A1, IP2_3_0)
#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2_3_0, A1),
#define GPSR1_1 F_(A1, IP2_3_0)
#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2_3_0, A1),
#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0_7_4, A1),
#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0_7_4, A1),
#define GPSR1_1 F_(A1, IP3_3_0)
#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP3_3_0, A1),
#define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0SR1_7_4, A1),
GPIO_FN(A1),
GPIO_FN(A1),
GPIO_FN(A1),
GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
PINMUX_IPSR_GPSR(IP0_3_2, A1),
GPIO_FN(A1),
u16 A1;