arch/mips/kernel/cevt-bcm1480.c

130

IOADDR(A_BCM1480_IMR_REGISTER(cpu,

arch/mips/kernel/cevt-bcm1480.c

36

cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

arch/mips/kernel/cevt-bcm1480.c

37

init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));

arch/mips/kernel/cevt-bcm1480.c

50

cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

arch/mips/kernel/cevt-bcm1480.c

62

cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

arch/mips/kernel/cevt-bcm1480.c

63

init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));

arch/mips/kernel/cevt-bcm1480.c

85

cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

arch/mips/kernel/cevt-sb1250.c

130

IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +

arch/mips/kernel/cevt-sb1250.c

33

cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG));

arch/mips/kernel/cevt-sb1250.c

46

cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

arch/mips/kernel/cevt-sb1250.c

47

init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));

arch/mips/kernel/cevt-sb1250.c

61

cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

arch/mips/kernel/cevt-sb1250.c

62

init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));

arch/mips/kernel/cevt-sb1250.c

84

cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

arch/mips/kernel/csrc-bcm1480.c

21

return (u64) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));

arch/mips/kernel/csrc-bcm1480.c

34

return __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));

arch/mips/kernel/csrc-bcm1480.c

43

plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));

arch/mips/kernel/csrc-sb1250.c

29

addr = IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT));

arch/mips/kernel/csrc-sb1250.c

59

IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,

arch/mips/kernel/csrc-sb1250.c

62

IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,

arch/mips/kernel/csrc-sb1250.c

65

IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,

arch/mips/mm/cerr-sb1.c

139

status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));

arch/mips/mm/cerr-sb1.c

142

l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));

arch/mips/mm/cerr-sb1.c

144

l2_tag = in64(IOADDR(A_L2_ECC_TAG));

arch/mips/mm/cerr-sb1.c

146

memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));

arch/mips/mm/cerr-sb1.c

172

csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));

arch/mips/mm/page.c

630

__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));

arch/mips/mm/page.c

636

while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))

arch/mips/mm/page.c

639

__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));

arch/mips/mm/page.c

657

__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));

arch/mips/mm/page.c

663

while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))

arch/mips/mm/page.c

666

__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));

arch/mips/pci/pci-bcm1480.c

210

reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));

arch/mips/pci/pci-sb1250.c

219

reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));

arch/mips/sibyte/bcm1480/irq.c

101

cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));

arch/mips/sibyte/bcm1480/irq.c

106

____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));

arch/mips/sibyte/bcm1480/irq.c

111

cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));

arch/mips/sibyte/bcm1480/irq.c

113

____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));

arch/mips/sibyte/bcm1480/irq.c

157

pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],

arch/mips/sibyte/bcm1480/irq.c

168

__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),

arch/mips/sibyte/bcm1480/irq.c

172

__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));

arch/mips/sibyte/bcm1480/irq.c

249

IOADDR(A_BCM1480_IMR_REGISTER(cpu,

arch/mips/sibyte/bcm1480/irq.c

258

IOADDR(A_BCM1480_IMR_REGISTER(cpu,

arch/mips/sibyte/bcm1480/irq.c

271

__raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +

arch/mips/sibyte/bcm1480/irq.c

279

IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));

arch/mips/sibyte/bcm1480/irq.c

281

IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));

arch/mips/sibyte/bcm1480/irq.c

288

__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));

arch/mips/sibyte/bcm1480/irq.c

292

__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));

arch/mips/sibyte/bcm1480/irq.c

320

IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));

arch/mips/sibyte/bcm1480/irq.c

322

IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));

arch/mips/sibyte/bcm1480/irq.c

53

cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));

arch/mips/sibyte/bcm1480/irq.c

55

____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));

arch/mips/sibyte/bcm1480/irq.c

70

cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));

arch/mips/sibyte/bcm1480/irq.c

72

____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));

arch/mips/sibyte/bcm1480/setup.c

110

sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));

arch/mips/sibyte/bcm1480/setup.c

120

plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));

arch/mips/sibyte/bcm1480/smp.c

26

IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

arch/mips/sibyte/bcm1480/smp.c

27

IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

arch/mips/sibyte/bcm1480/smp.c

28

IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

arch/mips/sibyte/bcm1480/smp.c

29

IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

arch/mips/sibyte/bcm1480/smp.c

33

IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

arch/mips/sibyte/bcm1480/smp.c

34

IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

arch/mips/sibyte/bcm1480/smp.c

35

IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

arch/mips/sibyte/bcm1480/smp.c

36

IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

arch/mips/sibyte/bcm1480/smp.c

40

IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

arch/mips/sibyte/bcm1480/smp.c

41

IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

arch/mips/sibyte/bcm1480/smp.c

42

IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

arch/mips/sibyte/bcm1480/smp.c

43

IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

arch/mips/sibyte/common/bus_watcher.c

161

csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/bus_watcher.c

162

csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/bus_watcher.c

166

(long long)__raw_readq(IOADDR(A_SCD_TRACE_READ)));

arch/mips/sibyte/common/bus_watcher.c

168

csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/bus_watcher.c

169

csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/bus_watcher.c

173

stats->status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));

arch/mips/sibyte/common/bus_watcher.c

176

stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS));

arch/mips/sibyte/common/bus_watcher.c

181

csr_out32(0, IOADDR(A_BUS_L2_ERRORS));

arch/mips/sibyte/common/bus_watcher.c

183

stats->memio_err = cntr = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));

arch/mips/sibyte/common/bus_watcher.c

187

csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS));

arch/mips/sibyte/common/bus_watcher.c

220

IOADDR(A_SCD_TRACE_SEQUENCE_0));

arch/mips/sibyte/common/bus_watcher.c

221

csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/bus_watcher.c

222

csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/bus_watcher.c

73

status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));

arch/mips/sibyte/common/bus_watcher.c

77

status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG));

arch/mips/sibyte/common/bus_watcher.c

87

l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));

arch/mips/sibyte/common/bus_watcher.c

88

memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));

arch/mips/sibyte/common/sb_tbprof.c

152

__raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));

arch/mips/sibyte/common/sb_tbprof.c

153

scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));

arch/mips/sibyte/common/sb_tbprof.c

164

IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));

arch/mips/sibyte/common/sb_tbprof.c

169

IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));

arch/mips/sibyte/common/sb_tbprof.c

176

IOADDR(A_SCD_PERF_CNT_CFG));

arch/mips/sibyte/common/sb_tbprof.c

178

__raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));

arch/mips/sibyte/common/sb_tbprof.c

180

__raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/sb_tbprof.c

185

__raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/sb_tbprof.c

200

IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/sb_tbprof.c

206

p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));

arch/mips/sibyte/common/sb_tbprof.c

208

p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));

arch/mips/sibyte/common/sb_tbprof.c

210

p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));

arch/mips/sibyte/common/sb_tbprof.c

212

p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));

arch/mips/sibyte/common/sb_tbprof.c

214

p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));

arch/mips/sibyte/common/sb_tbprof.c

216

p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));

arch/mips/sibyte/common/sb_tbprof.c

222

IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/sb_tbprof.c

232

__raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));

arch/mips/sibyte/common/sb_tbprof.c

272

scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));

arch/mips/sibyte/common/sb_tbprof.c

276

IOADDR(A_SCD_PERF_CNT_CFG));

arch/mips/sibyte/common/sb_tbprof.c

295

IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +

arch/mips/sibyte/common/sb_tbprof.c

299

IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +

arch/mips/sibyte/common/sb_tbprof.c

304

__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));

arch/mips/sibyte/common/sb_tbprof.c

305

__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));

arch/mips/sibyte/common/sb_tbprof.c

306

__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));

arch/mips/sibyte/common/sb_tbprof.c

307

__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));

arch/mips/sibyte/common/sb_tbprof.c

309

__raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));

arch/mips/sibyte/common/sb_tbprof.c

310

__raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));

arch/mips/sibyte/common/sb_tbprof.c

311

__raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));

arch/mips/sibyte/common/sb_tbprof.c

312

__raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));

arch/mips/sibyte/common/sb_tbprof.c

314

__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));

arch/mips/sibyte/common/sb_tbprof.c

315

__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));

arch/mips/sibyte/common/sb_tbprof.c

316

__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));

arch/mips/sibyte/common/sb_tbprof.c

317

__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));

arch/mips/sibyte/common/sb_tbprof.c

321

__raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));

arch/mips/sibyte/common/sb_tbprof.c

322

__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));

arch/mips/sibyte/common/sb_tbprof.c

323

__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));

arch/mips/sibyte/common/sb_tbprof.c

324

__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));

arch/mips/sibyte/common/sb_tbprof.c

325

__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));

arch/mips/sibyte/common/sb_tbprof.c

326

__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));

arch/mips/sibyte/common/sb_tbprof.c

327

__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));

arch/mips/sibyte/common/sb_tbprof.c

328

__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));

arch/mips/sibyte/common/sb_tbprof.c

333

IOADDR(A_SCD_TRACE_SEQUENCE_0));

arch/mips/sibyte/common/sb_tbprof.c

337

IOADDR(A_SCD_TRACE_SEQUENCE_1));

arch/mips/sibyte/common/sb_tbprof.c

338

__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));

arch/mips/sibyte/common/sb_tbprof.c

339

__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));

arch/mips/sibyte/common/sb_tbprof.c

340

__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));

arch/mips/sibyte/common/sb_tbprof.c

341

__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));

arch/mips/sibyte/common/sb_tbprof.c

342

__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));

arch/mips/sibyte/common/sb_tbprof.c

343

__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));

arch/mips/sibyte/common/sb_tbprof.c

348

IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));

arch/mips/sibyte/common/sb_tbprof.c

351

IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));

arch/mips/sibyte/sb1250/irq.c

100

cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +

arch/mips/sibyte/sb1250/irq.c

103

____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +

arch/mips/sibyte/sb1250/irq.c

139

pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],

arch/mips/sibyte/sb1250/irq.c

156

IOADDR(A_IMR_REGISTER(cpu,

arch/mips/sibyte/sb1250/irq.c

231

IOADDR(A_IMR_REGISTER(0,

arch/mips/sibyte/sb1250/irq.c

235

IOADDR(A_IMR_REGISTER(1,

arch/mips/sibyte/sb1250/irq.c

248

IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +

arch/mips/sibyte/sb1250/irq.c

251

IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +

arch/mips/sibyte/sb1250/irq.c

256

IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));

arch/mips/sibyte/sb1250/irq.c

258

IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));

arch/mips/sibyte/sb1250/irq.c

262

__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));

arch/mips/sibyte/sb1250/irq.c

263

__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));

arch/mips/sibyte/sb1250/irq.c

281

mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,

arch/mips/sibyte/sb1250/irq.c

47

cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +

arch/mips/sibyte/sb1250/irq.c

50

____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +

arch/mips/sibyte/sb1250/irq.c

61

cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +

arch/mips/sibyte/sb1250/irq.c

64

____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +

arch/mips/sibyte/sb1250/irq.c

88

cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +

arch/mips/sibyte/sb1250/irq.c

94

____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +

arch/mips/sibyte/sb1250/setup.c

175

sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));

arch/mips/sibyte/sb1250/setup.c

184

plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));

arch/mips/sibyte/sb1250/smp.c

21

IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),

arch/mips/sibyte/sb1250/smp.c

22

IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)

arch/mips/sibyte/sb1250/smp.c

26

IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),

arch/mips/sibyte/sb1250/smp.c

27

IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)

arch/mips/sibyte/sb1250/smp.c

31

IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),

arch/mips/sibyte/sb1250/smp.c

32

IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)

arch/mips/sibyte/swarm/rtc_m41t81.c

81

#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))

arch/mips/sibyte/swarm/rtc_xicor1241.c

56

#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))

arch/mips/sibyte/swarm/setup.c

160

reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3);

arch/xtensa/platforms/xt2000/include/platform/hardware.h

25

#define SONIC83934_ADDR IOADDR(0x0d030000)

arch/xtensa/platforms/xt2000/include/platform/hardware.h

41

#define XT2000_LED_ADDR IOADDR(0x0d040000)

arch/xtensa/platforms/xt2000/include/platform/serial.h

22

#define DUART16552_1_ADDR IOADDR(0x0d050020) /* channel 1 */

arch/xtensa/platforms/xt2000/include/platform/serial.h

23

#define DUART16552_2_ADDR IOADDR(0x0d050000) /* channel 2 */

arch/xtensa/platforms/xtfpga/include/platform/hardware.h

40

#define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000)

arch/xtensa/platforms/xtfpga/lcd.c

21

#define LCD_INSTR_ADDR ((char *)IOADDR(CONFIG_XTFPGA_LCD_BASE_ADDR))