IMR
IMR &= ~(1 << d->irq);
IMR |= (1 << d->irq);
IMR = ~0;
tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], IMR), &mask);
xe_mmio_write32(mmio, IMR(irqregs), ~bits);
xe_mmio_read32(mmio, IMR(irqregs));
xe_mmio_write32(mmio, IMR(irqregs), ~0);
xe_mmio_read32(mmio, IMR(irqregs));
u16 IMR;
.IMR = 0x2c,
.IMR = 0x2c,
*status = at91_adc_readl(st, IMR);
unsigned int IMR;
regs_buff[7] = macb_readl(bp, IMR);
queue->IMR = GEM_IMR(hw_q - 1);
queue->IMR = MACB_IMR;
iowrite32(0, ioaddr + IMR);
iowrite32(np->imrvalue, ioaddr + IMR);
iowrite32(0, ioaddr + IMR);
iowrite32(np->imrvalue, ioaddr + IMR);
iowrite32(0x0000, ioaddr + IMR);
iowrite32(np->imrvalue, ioaddr + IMR);
writel(0, dev->base + IMR);
writel(dev->IMR_cache, dev->base + IMR);
writel(dev->IMR_cache, dev->base + IMR);
writel(dev->IMR_cache, dev->base + IMR);
writel(dev->IMR_cache, dev->base + IMR);
writel(dev->IMR_cache, dev->base + IMR);
readl(dev->base + IMR);
writel(dev->IMR_cache, dev->base + IMR);
#define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
volatile __le32 IMR;
rtl818x_iowrite32(priv, &priv->map->IMR,
rtl818x_iowrite32(priv, &priv->map->IMR, 0);
__le32 IMR; /* 0x6c - Interrupt mask reg for 8187se */
IMR(CMPL_TIMEOUT) | \
IMR(PM_PME_RCVD) | \
IMR(PME_TO_ACK_RCVD) | \
IMR(MISC_CORRECTABLE) | \
IMR(NONFATAL) | \
IMR(FATAL) | \
IMR(LINK_DOWN) | \
IMR(HOT_RESET) | \
IMR(CFG_PCIE_TIMEOUT) | \
IMR(CFG_TIMEOUT) | \
IMR(CORRECTABLE) | \
IMR(NONFATAL) | \
IMR(FATAL) | \
IMR(CFG_ERR_POISON) | \
IMR(PME_TO_ACK_RCVD) | \
IMR(INTX) | \
IMR(PM_PME_RCVD) | \
IMR(SLV_UNSUPP) | \
IMR(SLV_UNEXP) | \
IMR(SLV_COMPL) | \
IMR(SLV_ERRP) | \
IMR(SLV_CMPABT) | \
IMR(SLV_ILLBUR) | \
IMR(MST_DECERR) | \
IMR(MST_SLVERR) | \
IMR(SLV_PCIE_TIMEOUT) \
IMR(LINK_DOWN) | \
IMR(HOT_RESET) | \
IMR(CFG_TIMEOUT) | \
IMR(CORRECTABLE) | \
IMR(NONFATAL) | \
IMR(FATAL) | \
IMR(INTX) | \
IMR(MSI) | \
IMR(SLV_UNSUPP) | \
IMR(SLV_UNEXP) | \
IMR(SLV_COMPL) | \
IMR(SLV_ERRP) | \
IMR(SLV_CMPABT) | \
IMR(SLV_ILLBUR) | \
IMR(MST_DECERR) | \
IMR(MST_SLVERR) | \
imr = spi_readl(as, IMR);
imr = spi_readl(as, IMR);
i810_writew(IMR, mmio, par->hw_state.imr);
par->hw_state.imr = i810_readw(IMR, mmio);
word = ac97c_readl(chip, IMR);
word = ac97c_readl(chip, IMR);
ac97c_writel(chip, IER, ac97c_readl(chip, IMR) | AC97C_SR_COEVT);
& (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
if (!purge && avs_platattr_test(adev, IMR)) {
irq = readl(kmb_i2s->i2s_base + IMR(i));
writel(irq, kmb_i2s->i2s_base + IMR(i));
status = ssc_readl(chip->ssc->regs, IMR);
ssc_readl(chip->ssc->regs, IMR);