IDR
writel(0xff, regs + ATMEL_TC_REG(2, IDR));
writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], IDR), ATMEL_TC_DEF_IRQS);
u16 IDR;
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY);
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN);
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN |
at91_adc_writel(st, IDR, 0xffffffff);
.IDR = 0x28,
.IDR = 0x28,
at91_adc_writel(st, IDR, BIT(channel));
at91_adc_writel(st, IDR,
#define GET_IDR(b) GET_GLOBAL_REG(IDR, (b))
#define GET_NM2VCBMT(b) GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
#define GET_HTW(b) GET_GLOBAL_FIELD(b, IDR, HTW)
#define GET_HUM(b) GET_GLOBAL_FIELD(b, IDR, HUM)
#define GET_TLBSIZE(b) GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
#define GET_NCB(b) GET_GLOBAL_FIELD(b, IDR, NCB)
#define GET_NIRPT(b) GET_GLOBAL_FIELD(b, IDR, NIRPT)
ssc_writel(ssc->regs, IDR, -1);
unsigned int IDR;
queue_writel(queue, IDR, bp->rx_intr_mask);
queue_writel(queue, IDR, MACB_BIT(TCOMP));
queue_writel(queue, IDR, bp->rx_intr_mask |
queue_writel(queue, IDR, MACB_BIT(WOL));
queue_writel(queue, IDR, GEM_BIT(WOL));
queue_writel(queue, IDR, -1);
queue_writel(queue, IDR, bp->rx_intr_mask);
queue_writel(queue, IDR, MACB_BIT(TCOMP));
queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
queue_writel(queue, IDR, -1);
queue->IDR = GEM_IDR(hw_q - 1);
queue->IDR = MACB_IDR;
macb_writel(lp, IDR, MACB_BIT(RCOMP) |
queue_writel(queue, IDR, -1);
queue_writel(bp->queues, IDR, GEM_BIT(WOL));
queue_writel(bp->queues, IDR, MACB_BIT(WOL));
queue_writel(queue, IDR,
ret = get_registers(dev, IDR, sizeof(node_id), node_id);
set_registers(dev, IDR, netdev->addr_len, netdev->dev_addr);
set_registers(dev, IDR, 6, netdev->dev_addr);
idr_low = mpam_read_partsel_reg(msc, IDR);
idr_high = mpam_read_partsel_reg(msc, IDR + 4);
__le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
#define InboundDoorbellReg MUnit.IDR
__le32 IDR; /* 20h | Inbound Doorbell Register */
events = src_readl(dev, MUnit.IDR);
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_1);
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_4);
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_2);
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_3);
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_6);
rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_5);
src_writel(dev, MUnit.IDR, 1 << 23);
val = src_readl(dev, MUnit.IDR);
src_writel(dev, MUnit.IDR, val);
src_readl(dev, MUnit.IDR);
val = src_readl(dev, MUnit.IDR);
src_writel(dev, MUnit.IDR, val);
src_readl(dev, MUnit.IDR);
val = src_readl(dev, MUnit.IDR);
src_writel(dev, MUnit.IDR, val);
src_readl(dev, MUnit.IDR);
val = src_readl(dev, MUnit.IDR);
src_writel(dev, MUnit.IDR, val);
src_readl(dev, MUnit.IDR);
val = src_readl(dev, MUnit.IDR);
src_writel(dev, MUnit.IDR, val);
src_readl(dev, MUnit.IDR);
src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT);
src_writel(dev, MUnit.IDR, IOP_SRC_RESET_MASK);
at91_usart_spi_writel(aus, IDR, US_IR_RXRDY);
at91_usart_spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS);
spi_writel(as, IDR, SPI_BIT(OVRES));
spi_writel(as, IDR, pending);
spi_writel(as, IDR, pending);
spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
spi_writel(as, IDR, pending);
spi_writel(as, IDR, SPI_BIT(OVRES));
ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
ssc_writel(chip->ssc->regs, IDR, SSC_BIT(IDR_ENDTX));