ICE_DBG_PTP
ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
ice_debug(hw, ICE_DBG_PTP,
ice_debug(hw, ICE_DBG_PTP,
ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts);
ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts);
ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d",
ice_debug(hw, ICE_DBG_PTP,
ice_debug(hw, ICE_DBG_PTP,
ice_debug(hw, ICE_DBG_PTP,
ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status);
ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_REG_GLOBAL for port %d, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Clearing soft reset bit for port %d, val: 0x%x\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Set soft reset bit for port %d, val: 0x%x\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Clear soft reset bit for port %d, val: 0x%x\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_REG_GLOBAL for port %d, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to soft reset port %d, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n");
ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n");
ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n");
ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",