GUEST_ASSERT_EQ
#define GUEST_ASSERT_REG_RAZ(reg) GUEST_ASSERT_EQ(read_sysreg_s(reg), 0)
GUEST_ASSERT_EQ(intid, timer_irq);
GUEST_ASSERT_EQ(timer_condition, istatus);
GUEST_ASSERT_EQ(FIELD_GET(SYS_PAR_EL1_ATTR, par), MAIR_ATTR_NORMAL); \
GUEST_ASSERT_EQ(FIELD_GET(SYS_PAR_EL1_SH, par), PTE_SHARED >> 8); \
GUEST_ASSERT_EQ(par & SYS_PAR_EL1_PA, TEST_ADDR); \
GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp));
GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp));
GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_svc));
GUEST_ASSERT_EQ(svc_addr, PC(bp_svc) + 4);
GUEST_ASSERT_EQ(sw_bp_addr, PC(bp_brk));
GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_brk));
GUEST_ASSERT_EQ(write_data, 'x');
GUEST_ASSERT_EQ(wp_data_addr, PC(write_data));
GUEST_ASSERT_EQ(ss_addr[0], PC(ss_start));
GUEST_ASSERT_EQ(ss_addr[1], PC(ss_start) + 4);
GUEST_ASSERT_EQ(ss_addr[2], PC(ss_start) + 8);
GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp2));
GUEST_ASSERT_EQ(hw_bp_addr, 0);
GUEST_ASSERT_EQ(write_data, 'x');
GUEST_ASSERT_EQ(wp_data_addr, 0);
GUEST_ASSERT_EQ(ss_addr[0], 0);
GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp_ctx));
GUEST_ASSERT_EQ(write_data, 'x');
GUEST_ASSERT_EQ(wp_data_addr, PC(write_data));
GUEST_ASSERT_EQ(bvr, w_bvr);
GUEST_ASSERT_EQ(wvr, w_wvr);
GUEST_ASSERT_EQ(regs->pc, expected_abort_pc);
GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_DABT_CUR);
GUEST_ASSERT_EQ(esr & ESR_ELx_FSC_TYPE, ESR_ELx_FSC_EXTABT);
GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_SERROR);
GUEST_ASSERT_EQ(ESR_ELx_ISS(esr), EXPECTED_SERROR_ISS);
GUEST_ASSERT_EQ(regs->pc, expected_abort_pc);
GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_DABT_CUR);
GUEST_ASSERT_EQ((esr & ESR_ELx_FSC), ESR_ELx_FSC_SEA_TTW(3));
GUEST_ASSERT_EQ(get_current_el(), 2);
GUEST_ASSERT_EQ(SYS_FIELD_GET(ID_AA64MMFR1_EL1, VH, mmfr1),
GUEST_ASSERT_EQ(SYS_FIELD_GET(ID_AA64MMFR0_EL1, FGT, mmfr0),
GUEST_ASSERT_EQ(e2h0, ID_AA64MMFR4_EL1_E2H0_NI_NV1);
GUEST_ASSERT_EQ(val, TEST_DATA);
GUEST_ASSERT_EQ(val, 0);
GUEST_ASSERT_EQ(par & 1, 0);
GUEST_ASSERT_EQ(val, 0);
GUEST_ASSERT_EQ(val, 0);
GUEST_ASSERT_EQ(addr, TEST_GVA);
GUEST_ASSERT_EQ(addr, TEST_GVA);
GUEST_ASSERT_EQ(*((uint64_t *)TEST_PTE_GVA) & PTE_AF, PTE_AF);
GUEST_ASSERT_EQ(ret, 0x77);
GUEST_ASSERT_EQ(val, TEST_DATA);
GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_DABT_CUR);
GUEST_ASSERT_EQ(esr & ESR_ELx_FSC_TYPE, ESR_ELx_FSC_EXTABT);
GUEST_ASSERT_EQ(esr & ESR_ELx_FnV, ESR_ELx_FnV);
GUEST_ASSERT_EQ(esr & ESR_ELx_FnV, 0);
GUEST_ASSERT_EQ(far, EINJ_GVA);
GUEST_ASSERT_EQ(gic_read_ap1r0(), 0);
GUEST_ASSERT_EQ(irq_handled, 0);
GUEST_ASSERT_EQ(irq_handled, num);
GUEST_ASSERT_EQ(irqnr_received[i], 1);
GUEST_ASSERT_EQ(gic_read_ap1r0(), 0);
GUEST_ASSERT_EQ(tmp, intid);
GUEST_ASSERT_EQ(gic_read_ap1r0(), 0);
GUEST_ASSERT_EQ(intid, MIN_SPI);
GUEST_ASSERT_EQ(GICR_TYPER_CPU_NUMBER(typer), cpu);
GUEST_ASSERT_EQ(vmreadz(VM_EXIT_REASON), EXIT_REASON_VMCALL);
GUEST_ASSERT_EQ(svm->vmcb->control.exit_code, SVM_EXIT_VMMCALL);
GUEST_ASSERT_EQ(intid, 1);
GUEST_ASSERT_EQ(intid, 1);
GUEST_ASSERT_EQ(val, MEM_TEST_VAL_2);
GUEST_ASSERT_EQ(intid, timer_irq);
GUEST_ASSERT_EQ(READ_ONCE(sw_bp_addr), LABEL_ADDRESS(sw_bp_2));
GUEST_ASSERT_EQ(irq_num, IRQ_PMU_OVF);
GUEST_ASSERT_EQ(ret.error, SBI_ERR_NOT_SUPPORTED);
GUEST_ASSERT_EQ(READ_ONCE(snapshot_data->ctr_overflow_mask), 0);
GUEST_ASSERT_EQ(READ_ONCE(snapshot_data->ctr_values[i]), 0);
GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum);
GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum);
GUEST_ASSERT_EQ(not_mapped, 0);
GUEST_ASSERT_EQ(set_storage_key(page_store_prot, 0x10), 0);
GUEST_ASSERT_EQ(set_storage_key(page_fetch_prot, 0x98), 0);
GUEST_ASSERT_EQ(val, 1);
GUEST_ASSERT_EQ(val, MMIO_VAL);
GUEST_ASSERT_EQ(val, 0);
GUEST_ASSERT_EQ(val, MMIO_VAL);
GUEST_ASSERT_EQ(READ_ONCE(st->rev), 0);
GUEST_ASSERT_EQ(READ_ONCE(st->attr), 0);
GUEST_ASSERT_EQ(status, 0);
GUEST_ASSERT_EQ(status, 0);
GUEST_ASSERT_EQ(status, 0);
GUEST_ASSERT_EQ(status, (ulong)st_gva[cpu]);
GUEST_ASSERT_EQ(READ_ONCE(st->flags), 0);
GUEST_ASSERT_EQ(READ_ONCE(st->preempted), 0);
GUEST_ASSERT_EQ(READ_ONCE(st->flags), 0);
GUEST_ASSERT_EQ(READ_ONCE(st->preempted), 0);
GUEST_ASSERT_EQ(rdmsr(MSR_KVM_STEAL_TIME), ((uint64_t)st_gva[cpu] | KVM_MSR_ENABLED));
GUEST_ASSERT_EQ(prepare_for_vmx_operation(vmx), true);
GUEST_ASSERT_EQ(load_vmcs(vmx), true);
GUEST_ASSERT_EQ(eax, guest_cpuid->entries[i].eax);
GUEST_ASSERT_EQ(ebx, guest_cpuid->entries[i].ebx);
GUEST_ASSERT_EQ(ecx, guest_cpuid->entries[i].ecx);
GUEST_ASSERT_EQ(edx, guest_cpuid->entries[i].edx);
GUEST_ASSERT_EQ(this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF), 0x40000001);
GUEST_ASSERT_EQ(v, ex_v); \
GUEST_ASSERT_EQ(vmreadz(VM_EXIT_REASON), EXIT_REASON_EXCEPTION_NMI);
GUEST_ASSERT_EQ((vmreadz(VM_EXIT_INTR_INFO) & 0xff), NMI_VECTOR);
GUEST_ASSERT_EQ(*output_gva, EXT_CAPABILITIES);
GUEST_ASSERT_EQ(res, hcall->expect);
GUEST_ASSERT_EQ(prepare_for_vmx_operation(vmx), true);
GUEST_ASSERT_EQ(load_vmcs(vmx), true);
GUEST_ASSERT_EQ(vector, GP_VECTOR);
GUEST_ASSERT_EQ(vector, GP_VECTOR);
GUEST_ASSERT_EQ(r, -KVM_ENOSYS);
GUEST_ASSERT_EQ(vmreadz(VM_EXIT_REASON), EXIT_REASON_VMCALL);
GUEST_ASSERT_EQ(svm->vmcb->control.exit_code, SVM_EXIT_VMMCALL);
GUEST_ASSERT_EQ(vmcb->save.rip, (u64)l2_instruction);
GUEST_ASSERT_EQ(i ? vmresume() : vmlaunch(), 0);
GUEST_ASSERT_EQ(vmreadz(GUEST_RIP), (u64)l2_instruction);
GUEST_ASSERT_EQ(ctrl->exit_code, SVM_EXIT_SHUTDOWN);
GUEST_ASSERT_EQ(vector == SS_VECTOR ? vmlaunch() : vmresume(), 0);
GUEST_ASSERT_EQ(vmreadz(VM_EXIT_REASON), EXIT_REASON_EXCEPTION_NMI);
GUEST_ASSERT_EQ((vmreadz(VM_EXIT_INTR_INFO) & 0xff), vector);
GUEST_ASSERT_EQ(vmreadz(VM_EXIT_INTR_ERROR_CODE), error_code);
GUEST_ASSERT_EQ(prepare_for_vmx_operation(vmx), true);
GUEST_ASSERT_EQ(load_vmcs(vmx), true);
GUEST_ASSERT_EQ(vmwrite(GUEST_IDTR_LIMIT, 0), 0);
GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_GP_DF), 0);
GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_DF), 0);
GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS), 0);
GUEST_ASSERT_EQ(vmreadz(VM_EXIT_REASON), EXIT_REASON_TRIPLE_FAULT);
GUEST_ASSERT_EQ(ctrl->exit_code, (SVM_EXIT_EXCP_BASE + vector));
GUEST_ASSERT_EQ(ctrl->exit_info_1, error_code);
GUEST_ASSERT_EQ(svm->vmcb->control.exit_code, SVM_EXIT_VMLOAD);
GUEST_ASSERT_EQ(svm->vmcb->control.exit_code, SVM_EXIT_VMMCALL);
GUEST_ASSERT_EQ(svm->vmcb->control.exit_code, SVM_EXIT_VMMCALL);
GUEST_ASSERT_EQ(rdmsr(MSR_KERNEL_GS_BASE), 0xbbbb);
GUEST_ASSERT_EQ(svm->vmcb->control.exit_code, SVM_EXIT_VMSAVE);
GUEST_ASSERT_EQ(svm->vmcb->control.exit_code, SVM_EXIT_VMLOAD);
GUEST_ASSERT_EQ(svm->vmcb->control.exit_code, SVM_EXIT_VMSAVE);
GUEST_ASSERT_EQ(msr_platform_info & MSR_PLATFORM_INFO_MAX_TURBO_RATIO,
GUEST_ASSERT_EQ(vector, GP_VECTOR);
GUEST_ASSERT_EQ(count, NUM_INSNS_RETIRED);
GUEST_ASSERT_EQ(count, NUM_BRANCH_INSNS_RETIRED);
GUEST_ASSERT_EQ(_rdpmc(pmc), count);
GUEST_ASSERT_EQ(_rdpmc(pmc), 0xdead);
GUEST_ASSERT_EQ(idx, gp_event.f.bit);
GUEST_ASSERT_EQ(global_ctrl, GENMASK_ULL(nr_gp_counters - 1, 0));
GUEST_ASSERT_EQ(global_ctrl, 0);
GUEST_ASSERT_EQ(get_bsp_flag(), 0);
GUEST_ASSERT_EQ(vector, PF_VECTOR);
GUEST_ASSERT_EQ(bounds[0], output[0]);
GUEST_ASSERT_EQ(bounds[1], output[1]);
GUEST_ASSERT_EQ(nmi_stage_get(), 1);
GUEST_ASSERT_EQ(regs->rip, (unsigned long)l2_guest_code_int);
GUEST_ASSERT_EQ(int_fired, 1);
GUEST_ASSERT_EQ(bp_fired, 1);
GUEST_ASSERT_EQ(nmi_stage_get(), 3);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val - HOST_ADJUST);
GUEST_ASSERT_EQ(count, 0);
GUEST_ASSERT_EQ((unsigned long)buffer, end);
GUEST_ASSERT_EQ(good_ipis_received, 2);
GUEST_ASSERT_EQ(xapic_read_reg(APIC_ISR + APIC_VECTOR_TO_REG_OFFSET(GOOD_IPI_VECTOR)),
GUEST_ASSERT_EQ(xapic_read_reg(APIC_ISR + APIC_VECTOR_TO_REG_OFFSET(GOOD_IPI_VECTOR)), 0);
GUEST_ASSERT_EQ(xapic_read_reg(APIC_ID), 1 << 24);
GUEST_ASSERT_EQ(good_ipis_received, 1);
GUEST_ASSERT_EQ(x2apic_read_reg(APIC_ISR + APIC_VECTOR_TO_REG_OFFSET(GOOD_IPI_VECTOR)),
GUEST_ASSERT_EQ(x2apic_read_reg(APIC_ISR + APIC_VECTOR_TO_REG_OFFSET(GOOD_IPI_VECTOR)), 0);
GUEST_ASSERT_EQ(x2apic_read_reg(APIC_ICR), val);
GUEST_ASSERT_EQ(tpr_guest_ppr_get(), tpr);
GUEST_ASSERT_EQ(tpr_guest_cr8_get(), tpr);
GUEST_ASSERT_EQ(tpr_guest_tpr_get(), 0);
GUEST_ASSERT_EQ(tpr_guest_irq_sync_val_get(), 0);
GUEST_ASSERT_EQ(tpr_guest_irq_sync_val_get(), 1);
GUEST_ASSERT_EQ(tpr_guest_irq_sync_val_get(), 1);
GUEST_ASSERT_EQ(tpr_guest_irq_sync_val_get(), 2);