arch/arm/mach-omap2/clockdomains33xx_data.c

20

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

28

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

36

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

44

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

52

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

60

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

68

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

76

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

84

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/clockdomains33xx_data.c

92

.cm_inst = AM33XX_CM_PER_MOD,

arch/arm/mach-omap2/cm33xx.h

34

#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)

arch/arm/mach-omap2/cm33xx.h

36

#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)

arch/arm/mach-omap2/cm33xx.h

38

#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)

arch/arm/mach-omap2/cm33xx.h

40

#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)

arch/arm/mach-omap2/cm33xx.h

42

#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)

arch/arm/mach-omap2/cm33xx.h

44

#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)

arch/arm/mach-omap2/cm33xx.h

46

#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)

arch/arm/mach-omap2/cm33xx.h

48

#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)

arch/arm/mach-omap2/cm33xx.h

50

#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)

arch/arm/mach-omap2/cm33xx.h

52

#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)

arch/arm/mach-omap2/cm33xx.h

54

#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)