arch/sh/boards/mach-hp6xx/pm.c

55

frqcr = __raw_readw(FRQCR);

arch/sh/boards/mach-hp6xx/pm.c

57

__raw_writew(frqcr, FRQCR);

arch/sh/boards/mach-hp6xx/pm.c

85

frqcr = __raw_readw(FRQCR);

arch/sh/boards/mach-hp6xx/pm.c

87

__raw_writew(frqcr, FRQCR);

arch/sh/boards/mach-hp6xx/pm.c

90

__raw_writew(frqcr, FRQCR);

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

44

return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

82

[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

84

[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

110

[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

112

[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh3/clock-sh3.c

28

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh3.c

40

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh3.c

52

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh3.c

64

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7705.c

32

clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];

arch/sh/kernel/cpu/sh3/clock-sh7705.c

41

int idx = __raw_readw(FRQCR) & 0x0003;

arch/sh/kernel/cpu/sh3/clock-sh7705.c

51

int idx = (__raw_readw(FRQCR) & 0x0300) >> 8;

arch/sh/kernel/cpu/sh3/clock-sh7705.c

61

int idx = (__raw_readw(FRQCR) & 0x0030) >> 4;

arch/sh/kernel/cpu/sh3/clock-sh7706.c

24

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7706.c

36

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7706.c

48

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7706.c

60

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7709.c

24

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7709.c

36

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7709.c

48

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7709.c

61

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7710.c

26

clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];

arch/sh/kernel/cpu/sh3/clock-sh7710.c

35

int idx = (__raw_readw(FRQCR) & 0x0007);

arch/sh/kernel/cpu/sh3/clock-sh7710.c

45

int idx = (__raw_readw(FRQCR) & 0x0700) >> 8;

arch/sh/kernel/cpu/sh3/clock-sh7710.c

55

int idx = (__raw_readw(FRQCR) & 0x0070) >> 4;

arch/sh/kernel/cpu/sh3/clock-sh7712.c

23

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7712.c

35

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh3/clock-sh7712.c

47

int frqcr = __raw_readw(FRQCR);

arch/sh/kernel/cpu/sh4/clock-sh4.c

28

clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007];

arch/sh/kernel/cpu/sh4/clock-sh4.c

37

int idx = (__raw_readw(FRQCR) & 0x0007);

arch/sh/kernel/cpu/sh4/clock-sh4.c

47

int idx = (__raw_readw(FRQCR) >> 3) & 0x0007;

arch/sh/kernel/cpu/sh4/clock-sh4.c

57

int idx = (__raw_readw(FRQCR) >> 6) & 0x0007;

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

109

[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

110

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

111

[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

112

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

113

[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

114

[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

67

mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

112

[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

113

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

114

[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

115

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

116

[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

117

[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

68

mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

114

[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

115

[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

116

[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

117

[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

118

[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

119

[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

71

mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

115

[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

116

[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

117

[DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

118

[DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

119

[DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

120

[DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

72

mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

63

SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7763.c

24

clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];

arch/sh/kernel/cpu/sh4a/clock-sh7763.c

33

int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);

arch/sh/kernel/cpu/sh4a/clock-sh7763.c

43

int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);

arch/sh/kernel/cpu/sh4a/clock-sh7763.c

70

int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);

arch/sh/kernel/cpu/sh4a/clock-sh7770.c

21

clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];

arch/sh/kernel/cpu/sh4a/clock-sh7770.c

30

int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);

arch/sh/kernel/cpu/sh4a/clock-sh7770.c

40

int idx = (__raw_readl(FRQCR) & 0x000f);

arch/sh/kernel/cpu/sh4a/clock-sh7770.c

50

int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);

arch/sh/kernel/cpu/sh4a/clock-sh7780.c

24

clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];

arch/sh/kernel/cpu/sh4a/clock-sh7780.c

33

int idx = (__raw_readl(FRQCR) & 0x0003);

arch/sh/kernel/cpu/sh4a/clock-sh7780.c

43

int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007);

arch/sh/kernel/cpu/sh4a/clock-sh7780.c

53

int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001);

arch/sh/kernel/cpu/sh4a/clock-sh7780.c

76

int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);