Symbol: FMT_CONTROL
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
227
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
231
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
237
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
476
REG_UPDATE_3(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
481
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
486
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
491
REG_UPDATE_3(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
512
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
516
REG_UPDATE(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
520
REG_UPDATE(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
524
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
589
REG_UPDATE(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
642
REG_UPDATE(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
646
REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
122
OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
131
OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
132
OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
133
OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
137
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
138
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
139
OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
143
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
144
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
145
OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
151
OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
152
OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
153
OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
154
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
155
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
156
OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
231
OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
289
uint32_t FMT_CONTROL;
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
46
SRI(FMT_CONTROL, FMT, id), \
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
88
SRI(FMT_CONTROL, FMT, id), \
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
171
REG_UPDATE_3(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
175
REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
178
REG_UPDATE_3(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
184
REG_UPDATE_3(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
194
REG_UPDATE(FMT_CONTROL, FMT_SUBSAMPLING_MODE, 0);
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
342
REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
380
opp_reg_state->fmt_control = REG_READ(FMT_CONTROL);
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
78
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
82
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
89
REG_UPDATE_2(FMT_CONTROL,
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h
38
SRI(FMT_CONTROL, FMT, id), \
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h
55
uint32_t FMT_CONTROL; \
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
385
opp_reg_state->fmt_control = REG_READ(FMT_CONTROL);
drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c
60
opp_reg_state->fmt_control = REG_READ(FMT_CONTROL);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
544
SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \