FIELD_MAX
n = n * 100 + ((x * 100) / FIELD_MAX(PLL_CTL1_FRAC));
(FIELD_MAX(ADF_VF2PF_SMALL_BLOCK_TYPE_MASK))
(FIELD_MAX(ADF_VF2PF_MEDIUM_BLOCK_TYPE_MASK) + \
(FIELD_MAX(ADF_VF2PF_LARGE_BLOCK_TYPE_MASK) + \
FIELD_MAX(ADF_VF2PF_SMALL_BLOCK_BYTE_MASK)
FIELD_MAX(ADF_VF2PF_MEDIUM_BLOCK_BYTE_MASK)
FIELD_MAX(ADF_VF2PF_LARGE_BLOCK_BYTE_MASK)
#define STM32_DMA3_MAX_BURST_LEN (1 + min_t(u32, FIELD_MAX(CTR1_SBL_1), \
FIELD_MAX(CTR1_DBL_1)))
#define REG_FIELD_MAX(__mask) ((u32)FIELD_MAX(__mask))
#define MAX_AB_VOTE (FIELD_MAX(AB_VOTE_MASK) - 1)
int max_ctx = FIELD_MAX(SW_CTX_ID);
max_ctx = FIELD_MAX(XEHP_SW_CTX_ID);
FIELD_MAX(VF2GUC_RESFIX_START_REQUEST_MSG_0_MARKER));
BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS);
(FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1);
#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD)
return ain <= FIELD_MAX(AD7124_CHANNEL_AINM);
if (tap > FIELD_MAX(AXI_ADC_DELAY_CTRL_MASK))
if (address > FIELD_MAX(AXI_DAC_CUSTOM_CTRL_ADDRESS))
if (val > FIELD_MAX(LP55xx_FADER_MAPPING_MASK)) {
FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) |
FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK)));
FIELD_MAX(RXFC_FS_MASK);
FIELD_MAX(RXFC_FS_MASK);
FIELD_MAX(TXBC_NDTB_MASK);
tdco = min(tdco, FIELD_MAX(RKCANFD_REG_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET));
FIELD_MAX(RKCANFD_REG_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE) + 1);
if (div > FIELD_MAX(A5PSW_MDIO_CFG_STATUS_CLKDIV) ||
#define ICE_MAX_I2C_DATA_SIZE FIELD_MAX(ICE_AQC_I2C_DATA_SIZE_M)
#define ETHER_TYPE_FULL_MASK cpu_to_be16(FIELD_MAX(U16_MAX))
if (ec->rx_coalesce_usecs > FIELD_MAX(FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT)) {
if (ec->tx_coalesce_usecs > FIELD_MAX(FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT)) {
FIELD_MAX(FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK) /
#define FBNIC_MBX_MAX_PAGE_SIZE FIELD_MAX(FBNIC_IPC_MBX_DESC_LEN_MASK)
if (size > FIELD_MAX(FBNIC_TWD_LEN_MASK))
if (size > FIELD_MAX(FBNIC_TWD_LEN_MASK))
#define EMAC_MAX_DELAY_UNIT FIELD_MAX(EMAC_TX_DLINE_CODE_MASK)
#define EMAC_RX_BUF_MAX FIELD_MAX(RX_DESC_1_BUFFER_SIZE_1_MASK)
val, FIELD_MAX(SYSCON_ETXDC_MASK));
val, FIELD_MAX(SYSCON_ERXDC_MASK));
btrl_max = FIELD_MAX(EST_XGMAC_BTRL);
btrl_max = FIELD_MAX(EST_GMAC5_BTRL);
timer = min(timer, FIELD_MAX(XAXIDMA_DELAY_MASK));
cap->max_average_mse = FIELD_MAX(KSZ9477_MMD_SQI_MASK);
next_seq_num = (seq_num + 1) & FIELD_MAX(CCCI_H_SEQ_FLD);
while (power > FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)) {
if (threshold_ns <= 1 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
} else if (threshold_ns <= 32 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
} else if (threshold_ns <= 1024 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
} else if (threshold_ns <= 32768 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
} else if (threshold_ns <= 1048576 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
} else if (threshold_ns <= (u64)33554432 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
*value = FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE);
max = FIELD_MAX(PA1_RG_VRT_SEL);
max = FIELD_MAX(PA1_RG_TERM_SEL);
max = FIELD_MAX(PA1_RG_INTR_CAL);
max = FIELD_MAX(PA6_RG_U2_DISCTH);
max = FIELD_MAX(PA6_RG_U2_PRE_EMP);
max = FIELD_MAX(P3A_RG_IEXT_INTR);
max = FIELD_MAX(P3D_RG_TX_IMPEL);
max = FIELD_MAX(P3D_RG_RX_IMPEL);
pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) *
*val = DIV_ROUND_UP(*val, FIELD_MAX(UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK));
*val = DIV_ROUND_UP(*val, FIELD_MAX(UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK));
#define UNCORE_MAX_RATIO FIELD_MAX(UNCORE_MAX_RATIO_MASK)
if (val > FIELD_MAX(UNCORE_EFF_LAT_CTRL_RATIO_MASK))
val *= FIELD_MAX(UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK);
val *= FIELD_MAX(UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK);
if (!input || input > FIELD_MAX(UNCORE_MAX_RATIO_MASK))
#define TOD_PERIOD_MAX FIELD_MAX(TOD_PERIOD_MASK)
#define TOD_DRIFT_ADJUST_FNS_MAX FIELD_MAX(TOD_DRIFT_ADJUST_MASK)
#define TOD_ADJUST_COUNT_MAX FIELD_MAX(TOD_ADJUST_COUNT_MASK)
if (cnt_period > FIELD_MAX(PWMDWIDTH_PERIOD) + 1) {
if (cnt_period >= ((FIELD_MAX(PWMDWIDTH_PERIOD) + 1) << FIELD_MAX(PWMCON_CLKDIV))) {
clkdiv = FIELD_MAX(PWMCON_CLKDIV);
cnt_period = FIELD_MAX(PWMDWIDTH_PERIOD) + 1;
clkdiv = ilog2(cnt_period) - ilog2(FIELD_MAX(PWMDWIDTH_PERIOD));
if (tmp > FIELD_MAX(RCAR_PWMCNT_CYC0_MASK))
tmp = FIELD_MAX(RCAR_PWMCNT_CYC0_MASK);
if (tmp > FIELD_MAX(RCAR_PWMCNT_PH0_MASK))
tmp = FIELD_MAX(RCAR_PWMCNT_PH0_MASK);
unsigned int max_wdlen = FIELD_MAX(SIMDR2_WDLEN1) + 1;
midi = min_t(u32, midi, FIELD_MAX(STM32H7_SPI_CFG2_MIDI));
if (intspec[0] > FIELD_MAX(HWIRQ_SID_MASK) || intspec[1] > FIELD_MAX(HWIRQ_PID_MASK) ||
intspec[2] > FIELD_MAX(HWIRQ_IRQID_MASK))
RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK)));
RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK)));
FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK));
max_div *= FIELD_MAX(ESP32S3_UART_SCLK_DIV_NUM);
wdog_dev->max_timeout = FIELD_MAX(WDT_TIMER_VAL) / airoha_wdt->wdt_freq;
#define IEEE80211_MAX_USF FIELD_MAX(LISTEN_INT_USF)
#define IEEE80211_MAX_UI FIELD_MAX(LISTEN_INT_UI)