drivers/accel/ivpu/ivpu_hw_ip.c

234

val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

236

val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

246

val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

248

val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);

drivers/dma/at_hdmac.c

1933

dma_writel(atdma, EN, 0);

drivers/dma/at_hdmac.c

2075

dma_writel(atdma, EN, AT_DMA_ENABLE);

drivers/dma/at_hdmac.c

2232

dma_writel(atdma, EN, AT_DMA_ENABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7034

WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4390

WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3260

WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2258

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2946

tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4556

WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3688

WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4074

WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1965

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2326

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

192

data = REG_SET_FIELD(data, VCN_AGDB_CTRL0, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

198

data = REG_SET_FIELD(data, VCN_AGDB_CTRL1, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

204

data = REG_SET_FIELD(data, VCN_AGDB_CTRL2, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

210

data = REG_SET_FIELD(data, VCN_AGDB_CTRL3, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

222

data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

255

data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

43

DDC_GPIO_REG_LIST_ENTRY(EN, cd, id),\

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

66

DDC_GPIO_VGA_REG_LIST_ENTRY(EN, cd),\

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

83

DDC_GPIO_I2C_REG_LIST_ENTRY(EN, cd),\

drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h

40

GENERIC_GPIO_REG_LIST_ENTRY(EN, cd, id),\

drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h

48

HPD_GPIO_REG_LIST_ENTRY(EN, cd, id),\

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

114

REG_UPDATE(EN_reg, EN, ~value);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

151

REG_UPDATE(EN_reg, EN, 0);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

47

REG_GET(EN_reg, EN, &gpio->store.en);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

56

REG_UPDATE(EN_reg, EN, gpio->store.en);

drivers/gpu/drm/imx/dc/dc-fg.c

168

regmap_write(fg->reg, PKICKCONFIG, COL(kick_col) | ROW(kick_row) | EN);

drivers/gpu/drm/imx/dc/dc-fg.c

171

regmap_write(fg->reg, SKICKCONFIG, COL(kick_col) | ROW(kick_row) | EN);

drivers/gpu/drm/mediatek/mtk_dpi.c

204

mtk_dpi_mask(dpi, DPI_EN, EN, EN);

drivers/gpu/drm/mediatek/mtk_dpi.c

209

mtk_dpi_mask(dpi, DPI_EN, 0, EN);

drivers/gpu/drm/nouveau/gv100_fence.c

31

NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) |

drivers/gpu/drm/nouveau/gv100_fence.c

62

NVDEF(NVC36F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN) |

drivers/gpu/drm/nouveau/nvc0_fence.c

48

NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, EN) |

drivers/gpu/drm/radeon/trinity_dpm.c

715

WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN);

drivers/gpu/drm/radeon/trinity_dpm.c

745

WREG32_P(CG_CG_VOLTAGE_CNTL, EN, ~EN);

drivers/hwmon/as370-hwmon.c

41

val |= EN;

drivers/net/ethernet/amd/xgbe/xgbe-i2c.c

40

XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);

drivers/net/ethernet/amd/xgbe/xgbe-i2c.c

61

XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);

drivers/net/ethernet/amd/xgbe/xgbe-i2c.c

62

if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c

122

HINIC_SQ_CTXT_CEQ_ATTR_SET(0, EN);

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c

177

rq_ctxt->ceq_attr = HINIC_RQ_CTXT_CEQ_ATTR_SET(0, EN) |

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

615

cpu_to_le32(RQ_CTXT_CEQ_ATTR_SET(0, EN) |

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

159

regmap_update_bits(regmap, reg, EN_MASK, EN);

drivers/pci/controller/dwc/pcie-qcom.c

1020

val |= EN;

drivers/pci/controller/dwc/pcie-qcom.c

637

val |= EN;

drivers/pci/controller/dwc/pcie-qcom.c

731

val |= EN;

drivers/regulator/mc13xxx.h

100

.enable_bit = prefix ## _reg ## _ ## _name ## EN, \

drivers/regulator/mc13xxx.h

67

.enable_bit = prefix ## _reg ## _ ## _name ## EN, \

drivers/regulator/mc13xxx.h

85

.enable_bit = prefix ## _reg ## _ ## _name ## EN, \

drivers/thermal/qcom/tsens-8960.c

143

reg |= mask | SLP_CLK_ENA | EN;

drivers/thermal/qcom/tsens-8960.c

145

reg |= mask | SLP_CLK_ENA_8660 | EN;

drivers/thermal/qcom/tsens-8960.c

162

mask |= EN;

drivers/thermal/qcom/tsens-8960.c

70

mask = SLP_CLK_ENA | EN;

drivers/thermal/qcom/tsens-8960.c

72

mask = SLP_CLK_ENA_8660 | EN;

sound/soc/renesas/rcar/ssi.c

575

ssi->cr_en = EN;