drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

554

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

42

#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

495

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

753

memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c

134

&anx6345->dpcd, DP_RECEIVER_CAP_SIZE);

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c

63

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c

647

&anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);

drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c

83

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1331

u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1356

u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2];

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1372

err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE);

drivers/gpu/drm/bridge/ite-it6505.c

452

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/bridge/synopsys/dw-dp.c

279

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/bridge/tc358767.c

359

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/bridge/tc358767.c

844

DP_RECEIVER_CAP_SIZE);

drivers/gpu/drm/display/drm_dp_helper.c

1074

bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1091

bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1178

static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

1189

u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

1191

u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/display/drm_dp_helper.c

1220

drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);

drivers/gpu/drm/display/drm_dp_helper.c

1241

u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

1245

ret = drm_dp_dpcd_read_data(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);

drivers/gpu/drm/display/drm_dp_helper.c

1255

drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);

drivers/gpu/drm/display/drm_dp_helper.c

1275

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1316

int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1345

int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1410

int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1453

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1509

bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1540

bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1571

bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1605

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1671

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1758

drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

1841

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

296

static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

3030

const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,

drivers/gpu/drm/display/drm_dp_helper.c

3064

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

3085

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

337

if (offset < DP_RECEIVER_CAP_SIZE) {

drivers/gpu/drm/display/drm_dp_helper.c

351

int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

3525

bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

3550

bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

358

int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

3648

int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

386

const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

410

const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/display/drm_dp_mst_topology.c

3616

const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/display/drm_dp_mst_topology.c

4970

seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf);

drivers/gpu/drm/display/drm_dp_mst_topology.c

6156

u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

42

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/i915/display/intel_display_types.h

1797

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/i915/display/intel_dp.c

6578

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

148

static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

198

static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

213

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

264

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

81

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/i915/display/intel_dp_link_training.c

97

const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.h

16

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1618

u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/i915/display/intel_dp_mst.c

1641

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

302

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/mediatek/mtk_dp.c

107

u8 rx_cap[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/msm/dp/dp_display.c

407

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/msm/dp/dp_panel.h

32

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/nouveau/include/nvif/if0012.h

243

__u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/nouveau/include/nvif/outp.h

107

int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],

drivers/gpu/drm/nouveau/nouveau_encoder.h

85

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/nouveau/nvif/outp.c

113

nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs,

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h

48

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/radeon/atombios_dp.c

37

#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE

drivers/gpu/drm/radeon/atombios_dp.c

540

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/radeon/atombios_dp.c

836

memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);

drivers/gpu/drm/radeon/radeon_mode.h

470

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/rockchip/cdn-dp-core.c

351

DP_RECEIVER_CAP_SIZE);

drivers/gpu/drm/rockchip/cdn-dp-core.h

103

u8 dpcd[DP_RECEIVER_CAP_SIZE];

drivers/gpu/drm/tegra/dp.c

172

u8 dpcd[DP_RECEIVER_CAP_SIZE], value;

drivers/gpu/drm/xlnx/zynqmp_dp.c

406

u8 dpcd[DP_RECEIVER_CAP_SIZE];

include/drm/display/drm_dp_helper.h

1013

bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

135

bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

include/drm/display/drm_dp_helper.h

136

bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

include/drm/display/drm_dp_helper.h

141

drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

147

drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

153

drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

160

drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

167

drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

174

drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

181

drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

188

drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

195

drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

202

drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

267

drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

273

drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

279

drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

287

drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

include/drm/display/drm_dp_helper.h

48

int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

50

int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

54

const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

include/drm/display/drm_dp_helper.h

57

const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

include/drm/display/drm_dp_helper.h

693

u8 dpcd[DP_RECEIVER_CAP_SIZE]);

include/drm/display/drm_dp_helper.h

713

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

715

bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

717

bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

720

int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

722

int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

725

int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

728

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

731

bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

733

bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

736

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

740

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

745

drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

754

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

759

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

762

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_helper.h

991

int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

include/drm/display/drm_dp_mst_helper.h

738

u8 dpcd[DP_RECEIVER_CAP_SIZE];

include/drm/display/drm_dp_mst_helper.h

855

enum drm_dp_mst_mode drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);