drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

281

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

35

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

287

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

35

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

247

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

32

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

159

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h

29

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

138

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

29

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

318

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

34

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h

154

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h

27

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h

148

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h

29

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

291

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

33

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

173

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

28

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

304

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

33

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

311

.clk_ctrl = DPU_CLK_CTRL_WB2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

32

[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },