drivers/gpu/drm/radeon/evergreen.c

3918

tmp = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/evergreen.c

3920

WREG32(DMA_RB_CNTL, tmp);

drivers/gpu/drm/radeon/evergreen.c

4027

tmp = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/evergreen.c

4029

WREG32(DMA_RB_CNTL, tmp);

drivers/gpu/drm/radeon/ni.c

1824

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1826

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/ni.c

1831

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1833

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/ni_dma.c

165

rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni_dma.c

167

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);

drivers/gpu/drm/radeon/ni_dma.c

170

rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni_dma.c

172

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);

drivers/gpu/drm/radeon/ni_dma.c

214

WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);

drivers/gpu/drm/radeon/ni_dma.c

245

WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);

drivers/gpu/drm/radeon/r600.c

1708

tmp = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

1710

WREG32(DMA_RB_CNTL, tmp);

drivers/gpu/drm/radeon/r600.c

1839

tmp = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

1841

WREG32(DMA_RB_CNTL, tmp);

drivers/gpu/drm/radeon/r600_dma.c

100

u32 rb_cntl = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/r600_dma.c

106

WREG32(DMA_RB_CNTL, rb_cntl);

drivers/gpu/drm/radeon/r600_dma.c

135

WREG32(DMA_RB_CNTL, rb_cntl);

drivers/gpu/drm/radeon/r600_dma.c

169

WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);

drivers/gpu/drm/radeon/si.c

3864

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3866

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

3870

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3872

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

4031

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

4033

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/si.c

4035

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

4037

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);