DMA_INT_ENAB
#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
csr |= DMA_INT_ENAB;
tmp &= ~DMA_INT_ENAB;
tmp |= DMA_INT_ENAB;
dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
dma_write32(val | DMA_INT_ENAB, DMA_CSR);
DMA_SCSI_DISAB | DMA_INT_ENAB);
dma_write32(val | DMA_INT_ENAB, DMA_CSR);
DMA_SCSI_DISAB | DMA_INT_ENAB)) &
dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);