DMA_ENABLE
#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
ioread32(denali->reg + DMA_ENABLE);
iowrite32(0, denali->reg + DMA_ENABLE);
val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
csr |= DMA_ENABLE;
esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
~(DMA_ST_WRITE | DMA_ENABLE));
val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
csr |= DMA_SCSI_DISAB | DMA_ENABLE;
csr |= DMA_ENABLE;
writel_relaxed(DMA_ENABLE, &chan->reg_chan->control);
if ((value & DMA_ENABLE) == 0)
if (readl_relaxed(&chan->reg_chan->control) & DMA_ENABLE) {
writel_relaxed(DMA_ENABLE, &dma->reg_tx_chan[i].control);
writel_relaxed(DMA_ENABLE, &dma->reg_rx_chan[i].control);
v = ~DMA_ENABLE & REG_MASK;
if (!(mstr_cfg & DMA_ENABLE)) {
mstr_cfg |= DMA_ENABLE;
if (mstr_cfg & DMA_ENABLE) {
mstr_cfg &= ~DMA_ENABLE;
mstr_cfg &= ~DMA_ENABLE;
BIT(DMA_ENABLE);
handshake(&dma->dmactl, BIT(DMA_ENABLE), 0, 50);
writel(readl(&dma->dmactl) & ~BIT(DMA_ENABLE), &dma->dmactl);
WARN_ON(readl(&dma->dmactl) & BIT(DMA_ENABLE));
writel(BIT(DMA_ENABLE), &dma->dmactl);