DMA_CTRL
ldma_update_bits(d, DMA_CTRL_RST, DMA_CTRL_RST, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
ldma_update_bits(d, mask, val, DMA_CTRL);
d->inst->name, readl(d->base + DMA_CTRL));
intel_uncore_write_fw(uncore, DMA_CTRL,
ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100, NULL);
intel_uncore_read_fw(uncore, DMA_CTRL));
intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
MMIO_D(DMA_CTRL);
xe_mmio_write32(mmio, DMA_CTRL,
ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl,
xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
[DMA_CTRL] = 0x04,
[DMA_CTRL] = 0x04,
[DMA_CTRL] = 0x00,
reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
bcmgenet_tdma_writel(priv, ring_mask, DMA_CTRL);
bcmgenet_rdma_writel(priv, ring_mask, DMA_CTRL);
reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
u32 DMA_CTRL;
rxdma = ioread32(&hw->reg->DMA_CTRL);
iowrite32(rxdma, &hw->reg->DMA_CTRL);
rxdma = ioread32(&hw->reg->DMA_CTRL);
iowrite32(rxdma, &hw->reg->DMA_CTRL);
dctrl = ioread32(&hw->reg->DMA_CTRL);
iowrite32(dctrl, &hw->reg->DMA_CTRL);
rxdma = ioread32(&hw->reg->DMA_CTRL);
iowrite32(rxdma, &hw->reg->DMA_CTRL);
ioread32(&hw->reg->DMA_CTRL));