DMA_CSR
csr = sbus_readl(lp->dregs + DMA_CSR);
sbus_writel(csr | DMA_RST_ENET, lp->dregs + DMA_CSR);
sbus_writel(csr & ~DMA_RST_ENET, lp->dregs + DMA_CSR);
u32 csr = sbus_readl(lp->dregs + DMA_CSR);
while (sbus_readl(lp->dregs + DMA_CSR) & DMA_FIFO_ISDRAIN)
csr = sbus_readl(lp->dregs + DMA_CSR);
sbus_writel(csr, lp->dregs + DMA_CSR);
printk("dcsr=%8.8x\n", sbus_readl(lp->dregs + DMA_CSR));
u32 csr = sbus_readl(lp->dregs + DMA_CSR);
sbus_writel(csr, lp->dregs + DMA_CSR);
u32 dma_csr = sbus_readl(lp->dregs + DMA_CSR);
sbus_writel(dma_csr, lp->dregs + DMA_CSR);
csr = sbus_readl(lp->dregs + DMA_CSR);
sbus_writel(csr | DMA_RST_ENET, lp->dregs + DMA_CSR);
sbus_writel(csr & ~DMA_RST_ENET, lp->dregs + DMA_CSR);
while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
dma_write32(val, DMA_CSR);
dma_write32(val, DMA_CSR);
csr = dma_read32(DMA_CSR);
dma_write32(csr, DMA_CSR);
u32 csr = dma_read32(DMA_CSR);
val = dma_read32(DMA_CSR);
dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
val = dma_read32(DMA_CSR);
dma_write32(val | DMA_RST_SCSI, DMA_CSR);
dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
val = dma_read32(DMA_CSR);
dma_write32(val | DMA_INT_ENAB, DMA_CSR);
csr = dma_read32(DMA_CSR);
dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
val = dma_read32(DMA_CSR);
dma_write32(val | DMA_RST_SCSI, DMA_CSR);
dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
dma_write32(DMA_RESET_FAS366, DMA_CSR);
dma_write32(DMA_RST_SCSI, DMA_CSR);
while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
dma_write32(0, DMA_CSR);
dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
val = dma_read32(DMA_CSR);
dma_write32(val | DMA_3CLKS, DMA_CSR);
val = dma_read32(DMA_CSR);
dma_write32(val, DMA_CSR);
val = dma_read32(DMA_CSR);
dma_write32(val, DMA_CSR);
val = dma_read32(DMA_CSR);
dma_write32(val | DMA_INT_ENAB, DMA_CSR);
csr = dma_read32(DMA_CSR);
dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
dma_write32(DMA_RST_SCSI, DMA_CSR);
dma_write32(0, DMA_CSR);
dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
dma_write32(val, DMA_CSR);
dma_write32(val, DMA_CSR);
dma_write32(csr, DMA_CSR);
csr = dma_read32(DMA_CSR);
dma_write32(csr, DMA_CSR);
u32 csr = dma_read32(DMA_CSR);
u32 val = dma_read32(DMA_CSR);
dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
val = dma_read32(DMA_CSR);
dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {