DMA_ATTR_WEAK_ORDERING
if (attrs & DMA_ATTR_WEAK_ORDERING)
if (attrs & DMA_ATTR_WEAK_ORDERING)
if (attrs & DMA_ATTR_WEAK_ORDERING)
imem->attrs = DMA_ATTR_WEAK_ORDERING |
dma_attr |= DMA_ATTR_WEAK_ORDERING;
DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);
DMA_ATTR_WEAK_ORDERING);
DMA_ATTR_WEAK_ORDERING);
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
(DMA_ATTR_WEAK_ORDERING | DMA_ATTR_SKIP_CPU_SYNC)
err = xsk_pool_dma_map(pool, pf->dev, DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);
xsk_pool_dma_unmap(pool, DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);
#define STMMAC_RX_DMA_ATTR (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
DMA_ATTR_WEAK_ORDERING)
{ DMA_ATTR_WEAK_ORDERING, "WEAK_ORDERING" }, \
#define IO_DMA_ATTR (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
DMA_ATTR_WEAK_ORDERING);
DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);
DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING);