drivers/gpu/drm/i915/display/i9xx_wm_regs.h

44

#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)

drivers/gpu/drm/i915/display/i9xx_wm_regs.h

55

#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)

drivers/gpu/drm/i915/display/i9xx_wm_regs.h

71

#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)

drivers/gpu/drm/i915/display/i9xx_wm_regs.h

9

#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)

drivers/gpu/drm/i915/display/intel_color_regs.h

33

#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \

drivers/gpu/drm/i915/display/intel_display_device.h

269

DISPLAY_MMIO_BASE((display)))

drivers/gpu/drm/i915/display/intel_display_device.h

274

DISPLAY_MMIO_BASE((display)))

drivers/gpu/drm/i915/display/intel_display_device.h

279

DISPLAY_MMIO_BASE((display)))

drivers/gpu/drm/i915/display/intel_display_regs.h

1140

#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1141

#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1142

#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

149

#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \

drivers/gpu/drm/i915/display/intel_display_regs.h

318

#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \

drivers/gpu/drm/i915/display/intel_display_regs.h

554

#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)

drivers/gpu/drm/i915/display/intel_display_regs.h

584

#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)

drivers/gpu/drm/i915/display/intel_display_regs.h

655

#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)

drivers/gpu/drm/i915/display/intel_gvt_api.c

32

return DISPLAY_MMIO_BASE(display);

drivers/gpu/drm/i915/display/intel_pfit_regs.h

10

#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)

drivers/gpu/drm/i915/display/intel_pfit_regs.h

31

#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)

drivers/gpu/drm/i915/display/intel_pfit_regs.h

39

#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)