Symbol: DCACHE_WAY_SIZE
arch/xtensa/include/asm/cache.h
26
#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
arch/xtensa/include/asm/cache.h
27
# define CACHE_WAY_SIZE DCACHE_WAY_SIZE
arch/xtensa/include/asm/cacheflush.h
156
#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/include/asm/cacheflush.h
69
#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/include/asm/cacheflush.h
95
((DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP))
arch/xtensa/include/asm/cachetype.h
8
#define cpu_dcache_is_aliasing() (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/include/asm/highmem.h
30
#if DCACHE_WAY_SIZE > PAGE_SIZE
arch/xtensa/include/asm/page.h
118
#if defined(CONFIG_MMU) && DCACHE_WAY_SIZE > PAGE_SIZE
arch/xtensa/include/asm/page.h
62
#if DCACHE_WAY_SIZE > PAGE_SIZE
arch/xtensa/include/asm/page.h
64
# define DCACHE_ALIAS_MASK (PAGE_MASK & (DCACHE_WAY_SIZE - 1))
arch/xtensa/include/asm/pgtable.h
181
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/include/asm/pgtable.h
290
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
arch/xtensa/include/asm/pgtable.h
70
#define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
arch/xtensa/include/asm/pgtable.h
71
#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
arch/xtensa/include/asm/pgtable.h
72
#define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
arch/xtensa/include/asm/shmparam.h
19
#define SHMLBA ((PAGE_SIZE > DCACHE_WAY_SIZE)? PAGE_SIZE : DCACHE_WAY_SIZE)
arch/xtensa/kernel/entry.S
1729
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/kernel/entry.S
1861
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
arch/xtensa/mm/cache.c
233
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/mm/cache.c
271
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/mm/cache.c
58
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/mm/highmem.c
15
#if DCACHE_WAY_SIZE > PAGE_SIZE
arch/xtensa/mm/misc.S
112
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
arch/xtensa/mm/misc.S
218
#if (DCACHE_WAY_SIZE > PAGE_SIZE)