drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

106

return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

122

return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

31

return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

67

upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg);

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

70

lower = xe_mmio_read32(__compat_uncore_to_mmio(uncore), lower_reg);

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

71

upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg);

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

82

xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);

drivers/gpu/drm/xe/tests/xe_mocs.c

58

reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i >> 1));

drivers/gpu/drm/xe/tests/xe_mocs.c

95

reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_debugfs.c

51

xe_mmio_read32(mmio, PUNIT_TELEMETRY_GUID),

drivers/gpu/drm/xe/xe_device.c

608

if (xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) {

drivers/gpu/drm/xe/xe_device.c

728

xe_assert(xe, xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL) &

drivers/gpu/drm/xe/xe_device.c

903

if (xe_mmio_read32(&gt->mmio, FUSE2) & PRODUCTION_HW)

drivers/gpu/drm/xe/xe_device_sysfs.c

232

val = xe_mmio_read32(xe_root_tile_mmio(xe), BMG_PCIE_CAP);

drivers/gpu/drm/xe/xe_execlist.c

166

lo = xe_mmio_read32(&gt->mmio, RING_EXECLIST_STATUS_LO(hwe->mmio_base));

drivers/gpu/drm/xe/xe_execlist.c

167

hi = xe_mmio_read32(&gt->mmio, RING_EXECLIST_STATUS_HI(hwe->mmio_base));

drivers/gpu/drm/xe/xe_execlist.c

78

xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base));

drivers/gpu/drm/xe/xe_ggtt.c

587

xe_mmio_read32(xe_root_tile_mmio(xe), VF_CAP_REG);

drivers/gpu/drm/xe/xe_gsc.c

185

return xe_mmio_read32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) &

drivers/gpu/drm/xe/xe_gsc.c

334

er_status = xe_mmio_read32(&gt->mmio, GSCI_TIMER_STATUS) & GSCI_TIMER_STATUS_VALUE;

drivers/gpu/drm/xe/xe_gsc.c

623

xe_mmio_read32(mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)),

drivers/gpu/drm/xe/xe_gsc.c

624

xe_mmio_read32(mmio, HECI_FWSTS2(MTL_GSC_HECI1_BASE)),

drivers/gpu/drm/xe/xe_gsc.c

625

xe_mmio_read32(mmio, HECI_FWSTS3(MTL_GSC_HECI1_BASE)),

drivers/gpu/drm/xe/xe_gsc.c

626

xe_mmio_read32(mmio, HECI_FWSTS4(MTL_GSC_HECI1_BASE)),

drivers/gpu/drm/xe/xe_gsc.c

627

xe_mmio_read32(mmio, HECI_FWSTS5(MTL_GSC_HECI1_BASE)),

drivers/gpu/drm/xe/xe_gsc.c

628

xe_mmio_read32(mmio, HECI_FWSTS6(MTL_GSC_HECI1_BASE)));

drivers/gpu/drm/xe/xe_gsc_proxy.c

69

u32 fwsts1 = xe_mmio_read32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE));

drivers/gpu/drm/xe/xe_gt.c

609

gt->info.gmdid = xe_mmio_read32(&gt->mmio, GMD_ID);

drivers/gpu/drm/xe/xe_gt_clock.c

59

c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);

drivers/gpu/drm/xe/xe_gt_idle.c

186

xe_mmio_read32(&gt->mmio, domain->reg_ctl));

drivers/gpu/drm/xe/xe_gt_idle.c

247

pg_enabled = xe_mmio_read32(&gt->mmio, POWERGATE_ENABLE);

drivers/gpu/drm/xe/xe_gt_idle.c

248

pg_status = xe_mmio_read32(&gt->mmio, POWERGATE_DOMAIN_STATUS);

drivers/gpu/drm/xe/xe_gt_mcr.c

316

xe_mmio_read32(mmio, MIRROR_FUSE3));

drivers/gpu/drm/xe/xe_gt_mcr.c

318

xe_mmio_read32(mmio, XEHP_FUSE4));

drivers/gpu/drm/xe/xe_gt_mcr.c

329

xe_mmio_read32(mmio, MIRROR_FUSE3));

drivers/gpu/drm/xe/xe_gt_mcr.c

341

~xe_mmio_read32(mmio, MIRROR_FUSE3));

drivers/gpu/drm/xe/xe_gt_mcr.c

351

xe_mmio_read32(&gt->mmio, MIRROR_FUSE3));

drivers/gpu/drm/xe/xe_gt_mcr.c

462

xe_mmio_read32(&gt->mmio, MIRROR_FUSE3));

drivers/gpu/drm/xe/xe_gt_mcr.c

770

val = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_gt_mcr.c

816

val = xe_mmio_read32(&gt->mmio, reg);

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

388

regs[n] = xe_mmio_read32(&mmio, MED_VF_SW_FLAG(n));

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

391

regs[n] = xe_mmio_read32(&mmio, VF_SW_FLAG(n));

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

186

*values++ = xe_mmio_read32(&gt->mmio, *regs++);

drivers/gpu/drm/xe/xe_gt_throttle.c

101

return xe_mmio_read32(&gt->mmio, reg) & mask;

drivers/gpu/drm/xe/xe_gt_topology.c

146

u32 fuse3 = xe_mmio_read32(mmio, MIRROR_FUSE3);

drivers/gpu/drm/xe/xe_gt_topology.c

152

u32 fuse_val = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);

drivers/gpu/drm/xe/xe_gt_topology.c

158

u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);

drivers/gpu/drm/xe/xe_gt_topology.c

176

u32 fuse4 = xe_mmio_read32(mmio, XEHP_FUSE4);

drivers/gpu/drm/xe/xe_gt_topology.c

29

fuse_val[i] = xe_mmio_read32(&gt->mmio, regs[i]);

drivers/gpu/drm/xe/xe_gt_topology.c

38

u32 reg_val = xe_mmio_read32(&gt->mmio, XELP_EU_ENABLE);

drivers/gpu/drm/xe/xe_guc.c

1091

xe_mmio_read32(mmio, GUC_HEADER_INFO));

drivers/gpu/drm/xe/xe_guc.c

1107

xe_mmio_read32(mmio, SOFT_SCRATCH(13)));

drivers/gpu/drm/xe/xe_guc.c

1135

*status = xe_mmio_read32(&gt->mmio, GUC_STATUS);

drivers/gpu/drm/xe/xe_guc.c

1358

msg = xe_mmio_read32(&gt->mmio, SOFT_SCRATCH(15));

drivers/gpu/drm/xe/xe_guc.c

1510

xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX));

drivers/gpu/drm/xe/xe_guc.c

1515

xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX));

drivers/gpu/drm/xe/xe_guc.c

1611

response_buf[i] = xe_mmio_read32(mmio, reply_reg);

drivers/gpu/drm/xe/xe_guc.c

1767

status = xe_mmio_read32(&gt->mmio, GUC_STATUS);

drivers/gpu/drm/xe/xe_guc.c

1782

i, xe_mmio_read32(&gt->mmio, SOFT_SCRATCH(i)));

drivers/gpu/drm/xe/xe_guc.c

1833

u32 val = xe_mmio_read32(&gt->mmio, GMD_ID);

drivers/gpu/drm/xe/xe_guc.c

938

guc_status = xe_mmio_read32(&gt->mmio, GUC_STATUS);

drivers/gpu/drm/xe/xe_guc.c

942

boot_hash_chk = xe_mmio_read32(&gt->mmio, BOOT_HASH_CHK);

drivers/gpu/drm/xe/xe_guc.c

986

guc_status = xe_mmio_read32(mmio, GUC_STATUS);

drivers/gpu/drm/xe/xe_guc_ads.c

866

xe_mmio_read32(&gt->mmio, DIST_DBS_POPULATED);

drivers/gpu/drm/xe/xe_guc_capture.c

1588

value = xe_mmio_read32(&hwe->gt->mmio, desc.reg);

drivers/gpu/drm/xe/xe_guc_engine_activity.c

319

reg = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);

drivers/gpu/drm/xe/xe_guc_pc.c

398

reg = xe_mmio_read32(&gt->mmio, MTL_MPA_FREQUENCY);

drivers/gpu/drm/xe/xe_guc_pc.c

400

reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPA_FREQUENCY);

drivers/gpu/drm/xe/xe_guc_pc.c

411

reg = xe_mmio_read32(&gt->mmio, MTL_MPE_FREQUENCY);

drivers/gpu/drm/xe/xe_guc_pc.c

413

reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPE_FREQUENCY);

drivers/gpu/drm/xe/xe_guc_pc.c

429

reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);

drivers/gpu/drm/xe/xe_guc_pc.c

438

reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);

drivers/gpu/drm/xe/xe_guc_pc.c

450

reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);

drivers/gpu/drm/xe/xe_guc_pc.c

463

reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);

drivers/gpu/drm/xe/xe_guc_pc.c

481

freq = xe_mmio_read32(&gt->mmio, MTL_MIRROR_TARGET_WP1);

drivers/gpu/drm/xe/xe_guc_pc.c

484

freq = xe_mmio_read32(&gt->mmio, GT_PERF_STATUS);

drivers/gpu/drm/xe/xe_guc_pc.c

497

freq = xe_mmio_read32(&gt->mmio, RPNSWREQ);

drivers/gpu/drm/xe/xe_guc_pc.c

757

reg = xe_mmio_read32(&gt->mmio, MTL_MIRROR_TARGET_WP1);

drivers/gpu/drm/xe/xe_guc_pc.c

768

reg = xe_mmio_read32(&gt->mmio, GT_CORE_STATUS);

drivers/gpu/drm/xe/xe_guc_pc.c

791

reg = xe_mmio_read32(&gt->mmio, GT_GFX_RC6);

drivers/gpu/drm/xe/xe_guc_pc.c

805

reg = xe_mmio_read32(&gt->mmio, MTL_MEDIA_MC6);

drivers/gpu/drm/xe/xe_guc_pc.c

818

reg = xe_mmio_read32(&gt->mmio, MTL_MEDIAP_STATE_CAP);

drivers/gpu/drm/xe/xe_guc_pc.c

820

reg = xe_mmio_read32(&gt->mmio, MTL_RP_STATE_CAP);

drivers/gpu/drm/xe/xe_guc_pc.c

836

reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);

drivers/gpu/drm/xe/xe_guc_pc.c

838

reg = xe_mmio_read32(&gt->mmio, RP_STATE_CAP);

drivers/gpu/drm/xe/xe_huc.c

235

return xe_mmio_read32(&gt->mmio, huc_auth_modes[type].reg) & huc_auth_modes[type].val;

drivers/gpu/drm/xe/xe_huc.c

313

xe_mmio_read32(&gt->mmio, HUC_KERNEL_LOAD_INFO));

drivers/gpu/drm/xe/xe_hw_engine.c

302

return xe_mmio_read32(&hwe->gt->mmio, reg);

drivers/gpu/drm/xe/xe_hw_engine.c

337

return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE;

drivers/gpu/drm/xe/xe_hw_engine.c

589

idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));

drivers/gpu/drm/xe/xe_hw_engine.c

590

maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));

drivers/gpu/drm/xe/xe_hw_engine.c

683

media_fuse = xe_mmio_read32(&gt->mmio, GT_VEBOX_VDBOX_DISABLE);

drivers/gpu/drm/xe/xe_hw_engine.c

721

xe_mmio_read32(&gt->mmio, MIRROR_FUSE3));

drivers/gpu/drm/xe/xe_hw_engine.c

737

xe_mmio_read32(&gt->mmio, SERVICE_COPY_ENABLE));

drivers/gpu/drm/xe/xe_hw_engine.c

797

ccs_mask = xe_mmio_read32(&gt->mmio, XEHP_FUSE4);

drivers/gpu/drm/xe/xe_hw_error.c

197

err_src = xe_mmio_read32(mmio, HEC_UNCORR_ERR_STATUS(base));

drivers/gpu/drm/xe/xe_hw_error.c

205

fw_err = xe_mmio_read32(mmio, HEC_UNCORR_FW_ERR_DW0(base));

drivers/gpu/drm/xe/xe_hw_error.c

288

vector = xe_mmio_read32(mmio, ERR_STAT_GT_VECTOR_REG(hw_err, i));

drivers/gpu/drm/xe/xe_hw_error.c

308

err_stat = xe_mmio_read32(mmio, ERR_STAT_GT_REG(hw_err));

drivers/gpu/drm/xe/xe_hw_error.c

349

slave_global_errstat = xe_mmio_read32(mmio, SOC_GLOBAL_ERR_STAT_REG(slave, hw_err));

drivers/gpu/drm/xe/xe_hw_error.c

352

slave_local_errstat = xe_mmio_read32(mmio, SOC_LOCAL_ERR_STAT_REG(slave, hw_err));

drivers/gpu/drm/xe/xe_hw_error.c

403

master_global_errstat = xe_mmio_read32(mmio, SOC_GLOBAL_ERR_STAT_REG(master, hw_err));

drivers/gpu/drm/xe/xe_hw_error.c

408

master_local_errstat = xe_mmio_read32(mmio, SOC_LOCAL_ERR_STAT_REG(master, hw_err));

drivers/gpu/drm/xe/xe_hw_error.c

441

err_src = xe_mmio_read32(&tile->mmio, DEV_ERR_STAT_REG(hw_err));

drivers/gpu/drm/xe/xe_hw_error.c

537

master_ctl = xe_mmio_read32(&tile->mmio, GFX_MSTR_IRQ);

drivers/gpu/drm/xe/xe_hwmon.c

1017

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));

drivers/gpu/drm/xe/xe_hwmon.c

1027

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));

drivers/gpu/drm/xe/xe_hwmon.c

1095

uval = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_hwmon.c

1111

uval = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_hwmon.c

1126

uval = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_hwmon.c

1131

uval = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_hwmon.c

1309

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_FAN_SPEED, channel));

drivers/gpu/drm/xe/xe_hwmon.c

1520

val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit);

drivers/gpu/drm/xe/xe_hwmon.c

355

reg_val = xe_mmio_read32(mmio, rapl_limit);

drivers/gpu/drm/xe/xe_hwmon.c

406

reg_val = xe_mmio_read32(mmio, rapl_limit);

drivers/gpu/drm/xe/xe_hwmon.c

477

reg_val = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_hwmon.c

522

xe_mmio_read32(mmio, PUNIT_TELEMETRY_GUID),

drivers/gpu/drm/xe/xe_hwmon.c

535

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS,

drivers/gpu/drm/xe/xe_hwmon.c

572

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,

drivers/gpu/drm/xe/xe_hwmon.c

716

uval = xe_mmio_read32(mmio, rapl_limit);

drivers/gpu/drm/xe/xe_hwmon.c

925

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel));

drivers/gpu/drm/xe/xe_hwmon.c

937

if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))

drivers/gpu/drm/xe/xe_i2c.c

261

*val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET));

drivers/gpu/drm/xe/xe_i2c.c

291

drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR));

drivers/gpu/drm/xe/xe_i2c.c

305

drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR));

drivers/gpu/drm/xe/xe_i2c.c

60

val[0] = xe_mmio_read32(mmio, REG_SG_REMAP_ADDR_PREFIX);

drivers/gpu/drm/xe/xe_i2c.c

61

val[1] = xe_mmio_read32(mmio, REG_SG_REMAP_ADDR_POSTFIX);

drivers/gpu/drm/xe/xe_irq.c

110

return xe_mmio_read32(mmio, GFX_MSTR_IRQ);

drivers/gpu/drm/xe/xe_irq.c

122

iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET));

drivers/gpu/drm/xe/xe_irq.c

135

xe_mmio_read32(mmio, GFX_MSTR_IRQ);

drivers/gpu/drm/xe/xe_irq.c

291

ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank));

drivers/gpu/drm/xe/xe_irq.c

370

intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank));

drivers/gpu/drm/xe/xe_irq.c

45

u32 val = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_irq.c

452

val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);

drivers/gpu/drm/xe/xe_irq.c

467

xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);

drivers/gpu/drm/xe/xe_irq.c

501

master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ);

drivers/gpu/drm/xe/xe_irq.c

54

xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_irq.c

56

xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_irq.c

77

xe_mmio_read32(mmio, IMR(irqregs));

drivers/gpu/drm/xe/xe_irq.c

87

xe_mmio_read32(mmio, IMR(irqregs));

drivers/gpu/drm/xe/xe_irq.c

93

xe_mmio_read32(mmio, IIR(irqregs));

drivers/gpu/drm/xe/xe_irq.c

95

xe_mmio_read32(mmio, IIR(irqregs));

drivers/gpu/drm/xe/xe_lrc.c

2648

val = xe_mmio_read32(&hwe->gt->mmio,

drivers/gpu/drm/xe/xe_lrc.c

2664

u32 val = xe_mmio_read32(&hwe->gt->mmio,

drivers/gpu/drm/xe/xe_mert.c

111

reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);

drivers/gpu/drm/xe/xe_mert.c

64

reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT);

drivers/gpu/drm/xe/xe_mmio.c

214

old = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_mmio.c

227

reg_val = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_mmio.c

274

oldudw = xe_mmio_read32(mmio, reg_udw);

drivers/gpu/drm/xe/xe_mmio.c

276

ldw = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_mmio.c

277

udw = xe_mmio_read32(mmio, reg_udw);

drivers/gpu/drm/xe/xe_mmio.c

302

read = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_mmio.c

328

read = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_mmio.h

23

u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mocs.c

279

reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

311

reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

384

reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

429

reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

511

reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

554

reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_nvm.c

51

return !(xe_mmio_read32(mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) &

drivers/gpu/drm/xe/xe_nvm.c

96

writable_override = (xe_mmio_read32(mmio, reg) & test_bit) == test_val;

drivers/gpu/drm/xe/xe_oa.c

1926

reg = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);

drivers/gpu/drm/xe/xe_oa.c

212

return xe_mmio_read32(&stream->gt->mmio, __oa_regs(stream)->oa_tail_ptr) &

drivers/gpu/drm/xe/xe_pat.c

378

u32 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

456

pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

514

pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

527

pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_PTA));

drivers/gpu/drm/xe/xe_pat.c

535

pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_ATS));

drivers/gpu/drm/xe/xe_pci.c

657

val = xe_mmio_read32(mmio, gmdid_reg);

drivers/gpu/drm/xe/xe_pci.c

834

mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR);

drivers/gpu/drm/xe/xe_pcode.c

45

err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK;

drivers/gpu/drm/xe/xe_pcode.c

80

if ((xe_mmio_read32(mmio, PCODE_MAILBOX) & PCODE_READY) != 0)

drivers/gpu/drm/xe/xe_pcode.c

93

*data0 = xe_mmio_read32(mmio, PCODE_DATA0);

drivers/gpu/drm/xe/xe_pcode.c

95

*data1 = xe_mmio_read32(mmio, PCODE_DATA1);

drivers/gpu/drm/xe/xe_pxp.c

118

return xe_mmio_read32(&gt->mmio, KCR_SIP) & BIT(id);

drivers/gpu/drm/xe/xe_query.c

101

upper = xe_mmio_read32(mmio, upper_reg);

drivers/gpu/drm/xe/xe_query.c

105

lower = xe_mmio_read32(mmio, lower_reg);

drivers/gpu/drm/xe/xe_query.c

108

upper = xe_mmio_read32(mmio, upper_reg);

drivers/gpu/drm/xe/xe_reg_sr.c

185

xe_mmio_read32(&gt->mmio, reg)) & (~entry->clr_bits);

drivers/gpu/drm/xe/xe_reg_sr.c

258

return xe_mmio_read32(&gt->mmio, reg);

drivers/gpu/drm/xe/xe_sriov.c

42

u32 value = xe_mmio_read32(xe_root_tile_mmio(xe), VF_CAP_REG);

drivers/gpu/drm/xe/xe_survivability_mode.c

132

info[id] = xe_mmio_read32(mmio, PCODE_SCRATCH(id));

drivers/gpu/drm/xe/xe_survivability_mode.c

385

data = xe_mmio_read32(mmio, PCODE_SCRATCH(0));

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

201

ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

306

ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

94

val[i] = xe_mmio_read32(sc->mmio, regs[i]);

drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c

112

ggc = xe_mmio_read32(xe_root_tile_mmio(xe), GGC);

drivers/gpu/drm/xe/xe_vram.c

156

reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id));

drivers/gpu/drm/xe/xe_vram.c

79

reg = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);

drivers/gpu/drm/xe/xe_wopcm.c

126

u32 reg_base = xe_mmio_read32(&gt->mmio, DMA_GUC_WOPCM_OFFSET);

drivers/gpu/drm/xe/xe_wopcm.c

127

u32 reg_size = xe_mmio_read32(&gt->mmio, GUC_WOPCM_SIZE);

drivers/gpu/drm/xe/xe_wopcm.c

172

xe_mmio_read32(&gt->mmio, DMA_GUC_WOPCM_OFFSET));

drivers/gpu/drm/xe/xe_wopcm.c

175

xe_mmio_read32(&gt->mmio, GUC_WOPCM_SIZE));