arch/arm64/include/asm/arch_gicv3.h

144

#define gic_write_irouter(v, c) writeq_relaxed(v, c)

arch/arm64/include/asm/arch_gicv3.h

146

#define gic_write_lpir(v, c) writeq_relaxed(v, c)

arch/arm64/include/asm/arch_gicv3.h

152

#define gits_write_baser(v, c) writeq_relaxed(v, c)

arch/arm64/include/asm/arch_gicv3.h

155

#define gits_write_cbaser(v, c) writeq_relaxed(v, c)

arch/arm64/include/asm/arch_gicv3.h

157

#define gits_write_cwriter(v, c) writeq_relaxed(v, c)

arch/arm64/include/asm/arch_gicv3.h

160

#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)

arch/arm64/include/asm/arch_gicv3.h

162

#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)

arch/arm64/include/asm/arch_gicv3.h

165

#define gicr_write_vpropbaser(v, c) writeq_relaxed(v, c)

arch/arm64/include/asm/arch_gicv3.h

168

#define gicr_write_vpendbaser(v, c) writeq_relaxed(v, c)

arch/arm64/kernel/acpi_parking_protocol.c

102

writeq_relaxed(__pa_symbol(secondary_entry),

arch/arm64/kernel/smp_spin_table.c

92

writeq_relaxed(pa_holding_pen, release_addr);

arch/mips/loongson64/smp.c

143

writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);

arch/mips/loongson64/smp.c

159

writeq_relaxed(startargs[3],

arch/mips/loongson64/smp.c

161

writeq_relaxed(startargs[2],

arch/mips/loongson64/smp.c

163

writeq_relaxed(startargs[1],

arch/mips/loongson64/smp.c

165

writeq_relaxed(startargs[0],

arch/sh/include/asm/io.h

56

#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })

drivers/acpi/cppc_acpi.c

1197

writeq_relaxed(val, vaddr);

drivers/bus/fsl-mc/mc-sys.c

109

writeq_relaxed(le64_to_cpu(cmd->params[i]), &portal->params[i]);

drivers/cache/sifive_ccache.c

162

writeq_relaxed(line, ccache_base + SIFIVE_CCACHE_FLUSH64);

drivers/clocksource/arm_arch_timer_mmio.c

72

writeq_relaxed(val, timer->base + CNTP_CVAL_LO);

drivers/clocksource/arm_arch_timer_mmio.c

83

writeq_relaxed(val, timer->base + CNTV_CVAL_LO);

drivers/clocksource/timer-clint.c

118

writeq_relaxed(clint_get_cycles64() + delta, r);

drivers/cpufreq/apple-soc-cpufreq.c

194

writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD);

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

134

writeq_relaxed(val, reg_base +

drivers/hwtracing/coresight/coresight-etm4x.h

594

writeq_relaxed((val), (csa)->base + (offset)); \

drivers/hwtracing/coresight/coresight-stm.c

321

writeq_relaxed(*(u64 *)data, addr);

drivers/hwtracing/intel_th/sth.c

45

writeq_relaxed(*(u64 *)payload, dest);

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

671

writeq_relaxed(*(val + i), dest + i);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4579

writeq_relaxed(doorbell, smmu->base + cfg[0]);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4590

writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4591

writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4594

writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4738

writeq_relaxed((dma & STRTAB_BASE_ADDR_MASK) | STRTAB_BASE_RA,

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4780

writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4805

writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4819

writeq_relaxed(smmu->priq.q.q_base,

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

1026

writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

459

writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, BASE));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

460

writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, CONS_INDX_BASE));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

487

writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE));

drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c

93

writeq_relaxed(val, reg);

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

212

writeq_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

213

writeq_relaxed(iova, tbu->base + DEBUG_VA_ADDR_REG);

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

215

writeq_relaxed(val, tbu->base + DEBUG_AXUSER_REG);

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

227

writeq_relaxed(val, tbu->base + DEBUG_TXN_TRIGG_REG);

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

253

writeq_relaxed(0, tbu->base + DEBUG_TXN_TRIGG_REG);

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

254

writeq_relaxed(0, tbu->base + DEBUG_VA_ADDR_REG);

drivers/iommu/arm/arm-smmu/arm-smmu.h

513

writeq_relaxed(val, arm_smmu_page(smmu, page) + offset);

drivers/iommu/arm/arm-smmu/qcom_iommu.c

99

writeq_relaxed(val, ctx->base + reg);

drivers/iommu/riscv/iommu.h

79

writeq_relaxed((val), (iommu)->reg + (addr))

drivers/irqchip/irq-gic-v3-its.c

4397

writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);

drivers/irqchip/irq-gic-v5-irs.c

50

writeq_relaxed(val, irs_data->irs_base + reg_offset);

drivers/irqchip/irq-gic-v5-its.c

61

writeq_relaxed(val, its_node->its_base + reg_offset);

drivers/irqchip/irq-ti-sci-inta.c

466

writeq_relaxed(BIT(event_desc->vint_bit),

drivers/net/ethernet/broadcom/asp2/bcmasp.h

439

writeq_relaxed(val, intf->m + off); \

drivers/net/ethernet/broadcom/bnge/bnge_txrx.h

26

writeq_relaxed(val, addr);

drivers/net/ethernet/broadcom/bnxt/bnxt.h

2894

writeq_relaxed(val, addr);

drivers/net/ethernet/cavium/thunder/nic_main.c

146

writeq_relaxed(msg[0], mbx_addr);

drivers/net/ethernet/cavium/thunder/nic_main.c

147

writeq_relaxed(msg[1], mbx_addr + 8);

drivers/net/ethernet/cavium/thunder/nic_main.c

149

writeq_relaxed(msg[1], mbx_addr + 8);

drivers/net/ethernet/cavium/thunder/nic_main.c

150

writeq_relaxed(msg[0], mbx_addr);

drivers/net/ethernet/cavium/thunder/nic_main.c

90

writeq_relaxed(val, nic->reg_base + offset);

drivers/net/ethernet/cavium/thunder/nicvf_main.c

108

writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT));

drivers/net/ethernet/cavium/thunder/nicvf_main.c

95

writeq_relaxed(val, nic->reg_base + offset);

drivers/net/ethernet/cavium/thunder/thunder_bgx.c

118

writeq_relaxed(val, addr);

drivers/net/ethernet/cavium/thunder/thunder_bgx.c

125

writeq_relaxed(val | readq_relaxed(addr), addr);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

102

writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

106

writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

130

writeq_relaxed(cfg, xcv->reg_base + XCV_CTL);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

135

writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

140

writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

143

writeq_relaxed(0x01, xcv->reg_base + XCV_BATCH_CRD_RET);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

148

writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

72

writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

77

writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

87

writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL);

drivers/net/ethernet/cavium/thunder/thunder_xcv.c

94

writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);

drivers/net/fddi/defza.c

93

#define writeq_u writeq_relaxed

drivers/perf/arm-cmn.c

1473

writeq_relaxed(CMN_CC_INIT, pmccntr);

drivers/perf/arm-cmn.c

1560

writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL);

drivers/perf/arm-cmn.c

1580

writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc));

drivers/perf/arm-cmn.c

1590

writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));

drivers/perf/arm-cmn.c

1591

writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));

drivers/perf/arm-cmn.c

1619

writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));

drivers/perf/arm-cmn.c

1620

writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));

drivers/perf/arm-cmn.c

1959

writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);

drivers/perf/arm-cmn.c

2125

writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);

drivers/perf/arm-cmn.c

2128

writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));

drivers/perf/arm-cmn.c

2129

writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));

drivers/perf/arm-cmn.c

2154

writeq_relaxed(0, CMN_DT_PMCCNTR(dtc));

drivers/perf/arm_smmuv3_pmu.c

734

writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);

drivers/perf/arm_smmuv3_pmu.c

746

writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);

drivers/perf/arm_smmuv3_pmu.c

785

writeq_relaxed(counter_present_mask,

drivers/perf/arm_smmuv3_pmu.c

787

writeq_relaxed(counter_present_mask,

drivers/perf/arm_smmuv3_pmu.c

789

writeq_relaxed(counter_present_mask,

drivers/perf/fujitsu_uncore_pmu.c

119

writeq_relaxed(PM_CR_RESET, uncorepmu->regs + PM_CR);

drivers/perf/fujitsu_uncore_pmu.c

121

writeq_relaxed(PM_CNTENCLR_RESET, uncorepmu->regs + PM_CNTENCLR);

drivers/perf/fujitsu_uncore_pmu.c

122

writeq_relaxed(PM_INTENCLR_RESET, uncorepmu->regs + PM_INTENCLR);

drivers/perf/fujitsu_uncore_pmu.c

123

writeq_relaxed(PM_OVSR_OVSRCLR_RESET, uncorepmu->regs + PM_OVSR);

drivers/perf/fujitsu_uncore_pmu.c

126

writeq_relaxed(PM_CNTCTL_RESET, uncorepmu->regs + PM_CNTCTL(i));

drivers/perf/fujitsu_uncore_pmu.c

127

writeq_relaxed(PM_EVTYPE_EVSEL(0), uncorepmu->regs + PM_EVTYPE(i));

drivers/perf/fujitsu_uncore_pmu.c

129

writeq_relaxed(PM_CR_ENABLE, uncorepmu->regs + PM_CR);

drivers/perf/fujitsu_uncore_pmu.c

143

writeq_relaxed(status, uncorepmu->regs + PM_OVSR);

drivers/perf/fujitsu_uncore_pmu.c

160

writeq_relaxed(PM_CR_ENABLE, to_uncore_pmu(pmu)->regs + PM_CR);

drivers/perf/fujitsu_uncore_pmu.c

165

writeq_relaxed(0, to_uncore_pmu(pmu)->regs + PM_CR);

drivers/perf/fujitsu_uncore_pmu.c

557

writeq_relaxed(0, uncorepmu->regs + PM_CR);

drivers/perf/fujitsu_uncore_pmu.c

76

writeq_relaxed(0, uncorepmu->regs + PM_EVCNTR(idx));

drivers/perf/fujitsu_uncore_pmu.c

79

writeq_relaxed(PM_EVTYPE_EVSEL(event->attr.config), uncorepmu->regs + PM_EVTYPE(idx));

drivers/perf/fujitsu_uncore_pmu.c

82

writeq_relaxed(PM_INTENSET_IDX(idx), uncorepmu->regs + PM_INTENSET);

drivers/perf/fujitsu_uncore_pmu.c

85

writeq_relaxed(PM_CNTCTL_RESET, uncorepmu->regs + PM_CNTCTL(idx));

drivers/perf/fujitsu_uncore_pmu.c

86

writeq_relaxed(PM_CNTENSET_IDX(idx), uncorepmu->regs + PM_CNTENSET);

drivers/perf/fujitsu_uncore_pmu.c

95

writeq_relaxed(PM_CNTENCLR_IDX(idx), uncorepmu->regs + PM_CNTENCLR);

drivers/perf/fujitsu_uncore_pmu.c

98

writeq_relaxed(PM_INTENCLR_IDX(idx), uncorepmu->regs + PM_INTENCLR);

drivers/perf/hisilicon/hisi_pcie_pmu.c

221

writeq_relaxed(val, pcie_pmu->base + offset);

drivers/perf/marvell_cn10k_ddr_pmu.c

1023

writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base +

drivers/perf/marvell_cn10k_ddr_pmu.c

509

writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base +

drivers/perf/marvell_cn10k_ddr_pmu.c

519

writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base +

drivers/perf/marvell_cn10k_ddr_pmu.c

547

writeq_relaxed(val, pmu->base + reg);

drivers/perf/marvell_cn10k_ddr_pmu.c

556

writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL,

drivers/perf/marvell_cn10k_ddr_pmu.c

649

writeq_relaxed(val, pmu->base + reg_offset);

drivers/perf/marvell_cn10k_ddr_pmu.c

702

writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base +

drivers/perf/marvell_cn10k_ddr_pmu.c

711

writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base +

drivers/perf/marvell_cn10k_ddr_pmu.c

748

writeq_relaxed(val, pmu->base + p_data->cnt_freerun_en);

drivers/perf/marvell_cn10k_ddr_pmu.c

762

writeq_relaxed(val, pmu->base + p_data->cnt_freerun_en);

drivers/perf/marvell_cn10k_ddr_pmu.c

771

writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl);

drivers/perf/marvell_cn10k_ddr_pmu.c

780

writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl);

drivers/perf/marvell_cn10k_ddr_pmu.c

802

writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl);

drivers/perf/marvell_cn10k_ddr_pmu.c

817

writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl);

drivers/perf/marvell_cn10k_ddr_pmu.c

826

writeq_relaxed(val, pmu->base + p_data->cnt_freerun_clr);

drivers/perf/marvell_cn10k_ddr_pmu.c

835

writeq_relaxed(val, pmu->base + p_data->cnt_freerun_clr);

drivers/perf/marvell_cn10k_tad_pmu.c

101

writeq_relaxed(0, tad_pmu->regions[i].base +

drivers/perf/marvell_cn10k_tad_pmu.c

109

writeq_relaxed(reg_val, tad_pmu->regions[i].base +

drivers/perf/marvell_cn10k_tad_pmu.c

80

writeq_relaxed(0, tad_pmu->regions[i].base +

drivers/resctrl/mpam_devices.c

1509

writeq_relaxed(0, regs + T241_SPARE_REG0_OFF);

drivers/resctrl/mpam_devices.c

1510

writeq_relaxed(0, regs + T241_SPARE_REG1_OFF);

drivers/soc/apple/mailbox.c

156

writeq_relaxed(msg.msg0, mbox->regs + mbox->hw->a2i_send0);

drivers/soc/apple/mailbox.c

157

writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg.msg1),

drivers/vfio/fsl-mc/vfio_fsl_mc.c

283

writeq_relaxed(cmd_data[i], ioaddr + i * sizeof(uint64_t));

include/asm-generic/io.h

417

#if defined(writeq) && !defined(writeq_relaxed)

include/asm-generic/io.h

418

#define writeq_relaxed writeq_relaxed

include/linux/coresight.h

563

writeq_relaxed(val, csa->base + offset);

include/linux/io-64-nonatomic-hi-lo.h

54

#ifndef writeq_relaxed

include/linux/io-64-nonatomic-lo-hi.h

54

#ifndef writeq_relaxed

rust/helpers/io.c

106

writeq_relaxed(value, addr);

tools/include/asm-generic/io.h

344

#if defined(writeq) && !defined(writeq_relaxed)

tools/include/asm-generic/io.h

345

#define writeq_relaxed writeq_relaxed

tools/testing/selftests/kvm/include/arm64/processor.h

248

#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c));})

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

439

writeq_relaxed(val, rdist_base + GICR_PROPBASER);

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

444

writeq_relaxed(val, rdist_base + GICR_PENDBASER);

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

27

writeq_relaxed(val, GITS_BASE_GVA + offset);