arch/x86/events/core.c

330

ret = wrmsrq_safe(reg, val);

arch/x86/events/intel/core.c

3434

wrmsrq_safe(x86_pmu_config_addr(idx), 0ull);

arch/x86/events/intel/core.c

3435

wrmsrq_safe(x86_pmu_event_addr(idx), 0ull);

arch/x86/events/intel/core.c

3440

wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);

arch/x86/events/intel/core.c

6527

if (wrmsrq_safe(msr, val_tmp) ||

arch/x86/events/intel/knc.c

186

(void)wrmsrq_safe(hwc->config_base + hwc->idx, val);

arch/x86/events/intel/knc.c

197

(void)wrmsrq_safe(hwc->config_base + hwc->idx, val);

arch/x86/events/intel/lbr.c

1606

if (wrmsrq_safe(MSR_ARCH_LBR_DEPTH, lbr_nr))

arch/x86/events/intel/p4.c

1401

wrmsrq_safe(reg, 0ULL);

arch/x86/events/intel/p4.c

915

(void)wrmsrq_safe(hwc->config_base,

arch/x86/events/intel/p4.c

948

(void)wrmsrq_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs);

arch/x86/events/intel/p4.c

949

(void)wrmsrq_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert);

arch/x86/events/intel/p4.c

983

(void)wrmsrq_safe(escr_addr, escr_conf);

arch/x86/events/intel/p4.c

984

(void)wrmsrq_safe(hwc->config_base,

arch/x86/events/intel/p6.c

167

(void)wrmsrq_safe(hwc->config_base, val);

arch/x86/events/intel/p6.c

184

(void)wrmsrq_safe(hwc->config_base, val);

arch/x86/include/asm/msr.h

250

return wrmsrq_safe(msr, (u64)high << 32 | low);

arch/x86/include/asm/msr.h

317

return wrmsrq_safe(msr_no, q);

arch/x86/kernel/cpu/amd.c

685

else if (c->x86 >= 0x19 && !wrmsrq_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {

arch/x86/kernel/cpu/amd.c

863

wrmsrq_safe(MSR_F15H_IC_CFG, value);

arch/x86/kernel/cpu/bus_lock.c

106

if (wrmsrq_safe(MSR_TEST_CTRL, ctrl))

arch/x86/kernel/cpu/common.c

170

wrmsrq_safe(info->msr_ppin_ctl, val | 2UL);

arch/x86/kernel/cpu/common.c

2277

wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);

arch/x86/kernel/cpu/common.c

2278

wrmsrq_safe(MSR_IA32_SYSENTER_ESP,

arch/x86/kernel/cpu/common.c

2280

wrmsrq_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);

arch/x86/kernel/cpu/common.c

2283

wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);

arch/x86/kernel/cpu/common.c

2284

wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 0ULL);

arch/x86/kernel/cpu/common.c

2285

wrmsrq_safe(MSR_IA32_SYSENTER_EIP, 0ULL);

arch/x86/kernel/cpu/mce/inject.c

751

wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), status);

arch/x86/kernel/cpu/mce/inject.c

753

wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/intel.c

466

wrmsrq_safe(MSR_ERROR_CONTROL, error_control);

arch/x86/kernel/cpu/resctrl/core.c

164

if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm))

arch/x86/kvm/svm/sev.c

3232

if (WARN_ON_ONCE(wrmsrq_safe(MSR_AMD64_VM_PAGE_FLUSH, addr | asid)))

arch/x86/kvm/x86.c

14099

else if (wrmsrq_safe(MSR_IA32_SPEC_CTRL, value))

arch/x86/kvm/x86.c

619

ret = wrmsrq_safe(msr, val);

arch/x86/kvm/x86.c

679

err = wrmsrq_safe(kvm_uret_msrs_list[slot], value);

arch/x86/lib/msr.c

62

return wrmsrq_safe(msr, m->q);

drivers/cpufreq/intel_pstate.c

1961

wrmsrq_safe(MSR_HWP_STATUS, 0);

drivers/platform/x86/intel/turbo_max_3.c

45

ret = wrmsrq_safe(MSR_OC_MAILBOX, value);

drivers/powercap/intel_rapl_msr.c

147

ra->err = wrmsrq_safe(ra->reg.msr, val);

drivers/thermal/intel/therm_throt.c

647

wrmsrq_safe(MSR_HWP_STATUS, 0);