write_dc
write_dc(par, DC_FB_ST_OFFSET, 0);
write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
write_dc(par, DC_LINE_SIZE,
write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) |
write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1) |
write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) |
write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1) |
write_dc(par, DC_DISPLAY_CFG, dcfg);
write_dc(par, DC_GENERAL_CFG, gcfg);
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
write_dc(par, DC_PAL_ADDRESS, regno);
write_dc(par, DC_PAL_DATA, val);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_DISPLAY_CFG, dcfg);
write_dc(par, DC_GENERAL_CFG, gcfg);
write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
write_dc(par, DC_GENERAL_CFG, val);
write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
write_dc(par, DC_GENLK_CTL, val);
write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
write_dc(par, DC_GENERAL_CFG, gcfg);
write_dc(par, DC_DISPLAY_CFG, val);
write_dc(par, DC_GENERAL_CFG, gcfg);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_FB_ST_OFFSET, 0);
write_dc(par, DC_CB_ST_OFFSET, 0);
write_dc(par, DC_CURS_ST_OFFSET, 0);
write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
write_dc(par, DC_IRQ_FILT_CTL, 0);
write_dc(par, DC_GENLK_CTL, val);
write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
write_dc(par, DC_DV_CTL, val | dv);
write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
write_dc(par, DC_H_BLANK_TIMING,
write_dc(par, DC_H_SYNC_TIMING,
write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
write_dc(par, DC_V_BLANK_TIMING,
write_dc(par, DC_V_SYNC_TIMING,
write_dc(par, DC_FB_ACTIVE,
write_dc(par, DC_DISPLAY_CFG, dcfg);
write_dc(par, DC_ARB_CFG, 0);
write_dc(par, DC_GENERAL_CFG, gcfg);
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
write_dc(par, DC_PAL_ADDRESS, regno);
write_dc(par, DC_PAL_DATA, val);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_PAL_ADDRESS, 0);
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, i, 0);
write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);
write_dc(par, i, par->dc[i]);
write_dc(par, DC_PAL_ADDRESS, 0);
write_dc(par, DC_PAL_DATA, par->dc_pal[i]);
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]);
write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]);
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]);
write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN |
write_dc(par, i, par->dc[i]);
write_dc(par, DC_PAL_ADDRESS, 0);
write_dc(par, DC_PAL_DATA, par->pal[i]);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] &
write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] &
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_PAL_ADDRESS, 0);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE |