arch/arm/kernel/hw_breakpoint.c

733

struct perf_event *wp, **slots;

arch/arm/kernel/hw_breakpoint.c

745

wp = slots[i];

arch/arm/kernel/hw_breakpoint.c

746

if (wp == NULL)

arch/arm/kernel/hw_breakpoint.c

757

info = counter_arch_bp(wp);

arch/arm/kernel/hw_breakpoint.c

758

info->trigger = wp->attr.bp_addr;

arch/arm/kernel/hw_breakpoint.c

764

if (!(access & hw_breakpoint_type(wp)))

arch/arm/kernel/hw_breakpoint.c

781

info = counter_arch_bp(wp);

arch/arm/kernel/hw_breakpoint.c

795

perf_bp_event(wp, regs);

arch/arm/kernel/hw_breakpoint.c

802

if (!is_default_overflow_handler(wp))

arch/arm/kernel/hw_breakpoint.c

805

enable_single_step(wp, instruction_pointer(regs));

arch/arm/kernel/hw_breakpoint.c

810

wp = slots[closest_match];

arch/arm/kernel/hw_breakpoint.c

811

info = counter_arch_bp(wp);

arch/arm/kernel/hw_breakpoint.c

814

perf_bp_event(wp, regs);

arch/arm/kernel/hw_breakpoint.c

815

if (is_default_overflow_handler(wp))

arch/arm/kernel/hw_breakpoint.c

816

enable_single_step(wp, instruction_pointer(regs));

arch/arm/kernel/hw_breakpoint.c

825

struct perf_event *wp, **slots;

arch/arm/kernel/hw_breakpoint.c

833

wp = slots[i];

arch/arm/kernel/hw_breakpoint.c

835

if (wp == NULL)

arch/arm/kernel/hw_breakpoint.c

838

info = counter_arch_bp(wp);

arch/arm/kernel/hw_breakpoint.c

847

disable_single_step(wp);

arch/arm64/kernel/hw_breakpoint.c

732

static int watchpoint_report(struct perf_event *wp, unsigned long addr,

arch/arm64/kernel/hw_breakpoint.c

735

int step = is_default_overflow_handler(wp);

arch/arm64/kernel/hw_breakpoint.c

736

struct arch_hw_breakpoint *info = counter_arch_bp(wp);

arch/arm64/kernel/hw_breakpoint.c

748

perf_bp_event(wp, regs);

arch/arm64/kernel/hw_breakpoint.c

759

struct perf_event *wp, **slots;

arch/arm64/kernel/hw_breakpoint.c

772

wp = slots[i];

arch/arm64/kernel/hw_breakpoint.c

773

if (wp == NULL)

arch/arm64/kernel/hw_breakpoint.c

782

if (!(access & hw_breakpoint_type(wp)))

arch/arm64/kernel/hw_breakpoint.c

798

step = watchpoint_report(wp, addr, regs);

arch/loongarch/kernel/hw_breakpoint.c

509

struct perf_event *wp, **slots;

arch/loongarch/kernel/hw_breakpoint.c

515

wp = slots[i];

arch/loongarch/kernel/hw_breakpoint.c

516

if (wp == NULL)

arch/loongarch/kernel/hw_breakpoint.c

518

perf_bp_event(wp, regs);

arch/powerpc/lib/sstep.c

788

const unsigned int *wp;

arch/powerpc/lib/sstep.c

835

wp = mem;

arch/powerpc/lib/sstep.c

838

reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);

arch/powerpc/lib/sstep.c

873

unsigned int *wp;

arch/powerpc/lib/sstep.c

932

wp = mem;

arch/powerpc/lib/sstep.c

935

*wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);

arch/powerpc/math-emu/math_efp.c

109

u32 wp[2];

arch/powerpc/math-emu/math_efp.c

200

vc.wp[0] = current->thread.evr[fc];

arch/powerpc/math-emu/math_efp.c

201

vc.wp[1] = regs->gpr[fc];

arch/powerpc/math-emu/math_efp.c

202

va.wp[0] = current->thread.evr[fa];

arch/powerpc/math-emu/math_efp.c

203

va.wp[1] = regs->gpr[fa];

arch/powerpc/math-emu/math_efp.c

204

vb.wp[0] = current->thread.evr[fb];

arch/powerpc/math-emu/math_efp.c

205

vb.wp[1] = regs->gpr[fb];

arch/powerpc/math-emu/math_efp.c

210

pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);

arch/powerpc/math-emu/math_efp.c

211

pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);

arch/powerpc/math-emu/math_efp.c

212

pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);

arch/powerpc/math-emu/math_efp.c

221

FP_UNPACK_SP(SA, va.wp + 1);

arch/powerpc/math-emu/math_efp.c

224

FP_UNPACK_SP(SB, vb.wp + 1);

arch/powerpc/math-emu/math_efp.c

227

FP_UNPACK_SP(SA, va.wp + 1);

arch/powerpc/math-emu/math_efp.c

236

vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

240

vc.wp[1] = va.wp[1] | SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

244

vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

278

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

282

FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,

arch/powerpc/math-emu/math_efp.c

302

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

305

FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,

arch/powerpc/math-emu/math_efp.c

313

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

316

FP_TO_INT_S(vc.wp[1], SB, 32,

arch/powerpc/math-emu/math_efp.c

329

FP_PACK_SP(vc.wp + 1, SR);

arch/powerpc/math-emu/math_efp.c

409

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

413

FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,

arch/powerpc/math-emu/math_efp.c

421

FP_UNPACK_SP(SB, vb.wp + 1);

arch/powerpc/math-emu/math_efp.c

444

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

447

FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,

arch/powerpc/math-emu/math_efp.c

455

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

458

FP_TO_INT_D(vc.wp[1], DB, 32,

arch/powerpc/math-emu/math_efp.c

496

FP_UNPACK_SP(SA0, va.wp);

arch/powerpc/math-emu/math_efp.c

497

FP_UNPACK_SP(SA1, va.wp + 1);

arch/powerpc/math-emu/math_efp.c

500

FP_UNPACK_SP(SB0, vb.wp);

arch/powerpc/math-emu/math_efp.c

501

FP_UNPACK_SP(SB1, vb.wp + 1);

arch/powerpc/math-emu/math_efp.c

504

FP_UNPACK_SP(SA0, va.wp);

arch/powerpc/math-emu/math_efp.c

505

FP_UNPACK_SP(SA1, va.wp + 1);

arch/powerpc/math-emu/math_efp.c

520

vc.wp[0] = va.wp[0] & ~SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

521

vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

525

vc.wp[0] = va.wp[0] | SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

526

vc.wp[1] = va.wp[1] | SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

530

vc.wp[0] = va.wp[0] ^ SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

531

vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;

arch/powerpc/math-emu/math_efp.c

569

vc.wp[0] = 0;

arch/powerpc/math-emu/math_efp.c

573

FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,

arch/powerpc/math-emu/math_efp.c

577

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

581

FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,

arch/powerpc/math-emu/math_efp.c

589

vc.wp[0] = 0;

arch/powerpc/math-emu/math_efp.c

592

FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,

arch/powerpc/math-emu/math_efp.c

596

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

599

FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,

arch/powerpc/math-emu/math_efp.c

607

vc.wp[0] = 0;

arch/powerpc/math-emu/math_efp.c

610

FP_TO_INT_S(vc.wp[0], SB0, 32,

arch/powerpc/math-emu/math_efp.c

614

vc.wp[1] = 0;

arch/powerpc/math-emu/math_efp.c

617

FP_TO_INT_S(vc.wp[1], SB1, 32,

arch/powerpc/math-emu/math_efp.c

633

FP_PACK_SP(vc.wp, SR0);

arch/powerpc/math-emu/math_efp.c

634

FP_PACK_SP(vc.wp + 1, SR1);

arch/powerpc/math-emu/math_efp.c

685

current->thread.evr[fc] = vc.wp[0];

arch/powerpc/math-emu/math_efp.c

686

regs->gpr[fc] = vc.wp[1];

arch/powerpc/math-emu/math_efp.c

691

pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);

arch/powerpc/math-emu/math_efp.c

692

pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);

arch/powerpc/math-emu/math_efp.c

693

pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);

arch/powerpc/math-emu/math_efp.c

757

fgpr.wp[0] = current->thread.evr[fc];

arch/powerpc/math-emu/math_efp.c

758

fgpr.wp[1] = regs->gpr[fc];

arch/powerpc/math-emu/math_efp.c

791

if (fgpr.wp[1] == 0)

arch/powerpc/math-emu/math_efp.c

799

if (fgpr.wp[1] == 0)

arch/powerpc/math-emu/math_efp.c

801

if (fgpr.wp[0] == 0)

arch/powerpc/math-emu/math_efp.c

810

if (fgpr.wp[1] == 0)

arch/powerpc/math-emu/math_efp.c

819

pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);

arch/powerpc/math-emu/math_efp.c

828

if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */

arch/powerpc/math-emu/math_efp.c

832

fgpr.wp[1]++; /* Z < 0, choose Z2 */

arch/powerpc/math-emu/math_efp.c

834

fgpr.wp[1]--; /* Z < 0, choose Z2 */

arch/powerpc/math-emu/math_efp.c

845

fgpr.wp[1]++; /* Z > 0, choose Z1 */

arch/powerpc/math-emu/math_efp.c

852

fgpr.wp[1]--; /* Z < 0, choose Z2 */

arch/powerpc/math-emu/math_efp.c

860

fgpr.wp[1]++; /* Z_low > 0, choose Z1 */

arch/powerpc/math-emu/math_efp.c

862

fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */

arch/powerpc/math-emu/math_efp.c

866

fgpr.wp[1]++; /* Z_low < 0, choose Z2 */

arch/powerpc/math-emu/math_efp.c

868

fgpr.wp[1]--; /* Z_low < 0, choose Z2 */

arch/powerpc/math-emu/math_efp.c

872

fgpr.wp[0]++; /* Z_high < 0, choose Z2 */

arch/powerpc/math-emu/math_efp.c

874

fgpr.wp[0]--; /* Z_high < 0, choose Z2 */

arch/powerpc/math-emu/math_efp.c

883

current->thread.evr[fc] = fgpr.wp[0];

arch/powerpc/math-emu/math_efp.c

884

regs->gpr[fc] = fgpr.wp[1];

arch/powerpc/math-emu/math_efp.c

886

pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);

arch/powerpc/platforms/pseries/dtl.c

68

struct dtl_entry *wp = dtlr->write_ptr;

arch/powerpc/platforms/pseries/dtl.c

71

if (!wp)

arch/powerpc/platforms/pseries/dtl.c

74

*wp = *dtle;

arch/powerpc/platforms/pseries/dtl.c

81

++wp;

arch/powerpc/platforms/pseries/dtl.c

82

if (wp == dtlr->buf_end)

arch/powerpc/platforms/pseries/dtl.c

83

wp = dtlr->buf;

arch/powerpc/platforms/pseries/dtl.c

84

dtlr->write_ptr = wp;

arch/s390/include/asm/nmi.h

60

u64 wp : 1; /* 20 psw mwp validity */

arch/x86/kvm/mmu/mmu.c

207

BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);

arch/x86/kvm/mmu/mmu.c

228

BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp);

arch/x86/kvm/mmu/mmu.c

5632

bool wp;

arch/x86/kvm/mmu/mmu.c

5639

wp = is_cr0_wp(mmu);

arch/x86/kvm/mmu/mmu.c

5662

check_write = check_pkey && wf && (uf || wp);

block/blk-zoned.c

1011

zone->wp = ULLONG_MAX;

block/blk-zoned.c

1013

zone->wp = sector;

block/blk-zoned.c

1024

zone->wp = sector + zwplug->wp_offset;

block/blk-zoned.c

2111

zwplug = disk_get_and_lock_zone_wplug(disk, zone->wp, GFP_NOIO, &flags);

block/blk-zoned.c

808

return zone->wp - zone->start;

block/blk-zoned.c

981

zone->wp = ULLONG_MAX;

block/blk-zoned.c

998

zone->wp = ULLONG_MAX;

drivers/accel/ivpu/ivpu_hw_btrs.c

217

static void wp_request_mtl(struct ivpu_device *vdev, struct wp_request *wp)

drivers/accel/ivpu/ivpu_hw_btrs.c

222

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

223

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

227

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

232

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

240

static void wp_request_lnl(struct ivpu_device *vdev, struct wp_request *wp)

drivers/accel/ivpu/ivpu_hw_btrs.c

245

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

246

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

250

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

251

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

255

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

256

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, wp->cdyn, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

264

static void wp_request(struct ivpu_device *vdev, struct wp_request *wp)

drivers/accel/ivpu/ivpu_hw_btrs.c

267

wp_request_mtl(vdev, wp);

drivers/accel/ivpu/ivpu_hw_btrs.c

269

wp_request_lnl(vdev, wp);

drivers/accel/ivpu/ivpu_hw_btrs.c

272

static int wp_request_send(struct ivpu_device *vdev, struct wp_request *wp)

drivers/accel/ivpu/ivpu_hw_btrs.c

282

wp_request(vdev, wp);

drivers/accel/ivpu/ivpu_hw_btrs.c

291

static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp, bool enable)

drivers/accel/ivpu/ivpu_hw_btrs.c

295

wp->min = hw->pll.min_ratio;

drivers/accel/ivpu/ivpu_hw_btrs.c

296

wp->max = hw->pll.max_ratio;

drivers/accel/ivpu/ivpu_hw_btrs.c

299

wp->target = enable ? hw->pll.pn_ratio : 0;

drivers/accel/ivpu/ivpu_hw_btrs.c

300

wp->cfg = enable ? hw->config : 0;

drivers/accel/ivpu/ivpu_hw_btrs.c

301

wp->cdyn = 0;

drivers/accel/ivpu/ivpu_hw_btrs.c

302

wp->epp = 0;

drivers/accel/ivpu/ivpu_hw_btrs.c

304

wp->target = hw->pll.pn_ratio;

drivers/accel/ivpu/ivpu_hw_btrs.c

305

wp->cfg = 0;

drivers/accel/ivpu/ivpu_hw_btrs.c

306

wp->cdyn = enable ? PLL_CDYN_DEFAULT : 0;

drivers/accel/ivpu/ivpu_hw_btrs.c

307

wp->epp = enable ? PLL_EPP_DEFAULT : 0;

drivers/accel/ivpu/ivpu_hw_btrs.c

334

struct wp_request wp;

drivers/accel/ivpu/ivpu_hw_btrs.c

342

prepare_wp_request(vdev, &wp, enable);

drivers/accel/ivpu/ivpu_hw_btrs.c

345

pll_ratio_to_dpu_freq(vdev, wp.target) / HZ_PER_MHZ, wp.cfg, wp.epp, wp.cdyn);

drivers/accel/ivpu/ivpu_hw_btrs.c

347

ret = wp_request_send(vdev, &wp);

drivers/acpi/resource.c

212

bool wp = addr->info.mem.write_protect;

drivers/acpi/resource.c

253

acpi_dev_memresource_flags(res, len, wp);

drivers/ata/libata-scsi.c

3724

u64 size, start, wp;

drivers/ata/libata-scsi.c

3734

wp = get_unaligned_le64(&rec[24]);

drivers/ata/libata-scsi.c

3739

put_unaligned_be64(wp, &rec[24]);

drivers/block/drbd/drbd_proc.c

222

char wp;

drivers/block/drbd/drbd_proc.c

270

wp = nc ? nc->wire_protocol - DRBD_PROT_A + 'A' : ' ';

drivers/block/drbd/drbd_proc.c

280

wp,

drivers/block/null_blk/null_blk.h

48

sector_t wp;

drivers/block/null_blk/zoned.c

137

zone->wp = zone->start + zone->len;

drivers/block/null_blk/zoned.c

158

zone->wp = zone->start + zone->capacity;

drivers/block/null_blk/zoned.c

161

zone->wp = zone->start;

drivers/block/null_blk/zoned.c

222

blkz.wp = zone->wp;

drivers/block/null_blk/zoned.c

249

sector + nr_sectors <= zone->wp)

drivers/block/null_blk/zoned.c

252

if (sector > zone->wp)

drivers/block/null_blk/zoned.c

255

return (zone->wp - sector) << SECTOR_SHIFT;

drivers/block/null_blk/zoned.c

275

if (zone->wp == zone->start) {

drivers/block/null_blk/zoned.c

379

zone->wp == NULL_ZONE_INVALID_WP) {

drivers/block/null_blk/zoned.c

383

sector = zone->wp;

drivers/block/null_blk/zoned.c

387

if (sector != zone->wp ||

drivers/block/null_blk/zoned.c

388

zone->wp + nr_sectors > zone->start + zone->capacity) {

drivers/block/null_blk/zoned.c

431

zone->wp += nr_sectors;

drivers/block/null_blk/zoned.c

432

if (zone->wp == zone->start + zone->capacity) {

drivers/block/null_blk/zoned.c

542

if (zone->wp > zone->start)

drivers/block/null_blk/zoned.c

548

if (zone->wp == zone->start)

drivers/block/null_blk/zoned.c

602

zone->wp = zone->start + zone->len;

drivers/block/null_blk/zoned.c

638

zone->wp = zone->start;

drivers/block/null_blk/zoned.c

760

zone->wp = zone->start;

drivers/block/null_blk/zoned.c

768

zone->wp = NULL_ZONE_INVALID_WP;

drivers/block/virtio_blk.c

598

zone.wp = virtio64_to_cpu(vblk->vdev, entry->z_wp);

drivers/block/virtio_blk.c

625

zone.wp = zone.start + zone.len;

drivers/block/virtio_blk.c

638

zone.wp = ULONG_MAX;

drivers/block/virtio_blk.c

642

zone.wp = ULONG_MAX;

drivers/block/zloop.c

106

sector_t wp;

drivers/block/zloop.c

190

zone->wp = zone->start;

drivers/block/zloop.c

193

zone->wp = ULLONG_MAX;

drivers/block/zloop.c

196

zone->wp = zone->start + file_sectors;

drivers/block/zloop.c

262

if (zone->wp == zone->start)

drivers/block/zloop.c

304

zone->wp = zone->start;

drivers/block/zloop.c

351

zone->wp = ULLONG_MAX;

drivers/block/zloop.c

452

zone->wp + nr_sectors > zone_end) {

drivers/block/zloop.c

458

sector = zone->wp;

drivers/block/zloop.c

461

} else if (sector != zone->wp) {

drivers/block/zloop.c

464

zone_no, sector, zone->wp);

drivers/block/zloop.c

480

zone->wp += nr_sectors;

drivers/block/zloop.c

481

if (zone->wp == zone_end) {

drivers/block/zloop.c

483

zone->wp = ULLONG_MAX;

drivers/block/zloop.c

687

zone->wp + nr_sectors > zone_end) {

drivers/block/zloop.c

692

rq->__sector = zone->wp;

drivers/block/zloop.c

693

zone->wp += blk_rq_sectors(rq);

drivers/block/zloop.c

694

if (zone->wp >= zone_end) {

drivers/block/zloop.c

696

zone->wp = ULLONG_MAX;

drivers/block/zloop.c

783

blkz.wp = zone->wp;

drivers/block/zloop.c

905

zone->wp = U64_MAX;

drivers/bus/mhi/common.h

266

__le64 wp __packed __aligned(4);

drivers/bus/mhi/common.h

281

__le64 wp __packed __aligned(4);

drivers/bus/mhi/common.h

292

__le64 wp __packed __aligned(4);

drivers/bus/mhi/ep/internal.h

102

__le64 wp __packed __aligned(4);

drivers/bus/mhi/ep/ring.c

213

memcpy_fromio(&val, (void __iomem *) &ring->ring_ctx->generic.wp, sizeof(u64));

drivers/bus/mhi/host/debugfs.c

121

le64_to_cpu(chan_ctxt->rp), le64_to_cpu(chan_ctxt->wp));

drivers/bus/mhi/host/debugfs.c

124

ring->rp, ring->wp,

drivers/bus/mhi/host/debugfs.c

73

le64_to_cpu(er_ctxt->wp));

drivers/bus/mhi/host/init.c

349

mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp;

drivers/bus/mhi/host/init.c

391

ring->rp = ring->wp = ring->base;

drivers/bus/mhi/host/init.c

393

er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase;

drivers/bus/mhi/host/init.c

395

ring->ctxt_wp = &er_ctxt->wp;

drivers/bus/mhi/host/init.c

420

ring->rp = ring->wp = ring->base;

drivers/bus/mhi/host/init.c

422

cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase;

drivers/bus/mhi/host/init.c

424

ring->ctxt_wp = &cmd_ctxt->wp;

drivers/bus/mhi/host/init.c

633

chan_ctxt->wp = 0;

drivers/bus/mhi/host/init.c

678

chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase;

drivers/bus/mhi/host/init.c

680

tre_ring->ctxt_wp = &chan_ctxt->wp;

drivers/bus/mhi/host/init.c

682

tre_ring->rp = tre_ring->wp = tre_ring->base;

drivers/bus/mhi/host/init.c

683

buf_ring->rp = buf_ring->wp = buf_ring->base;

drivers/bus/mhi/host/internal.h

216

void *wp;

drivers/bus/mhi/host/internal.h

232

void *wp;

drivers/bus/mhi/host/main.c

1106

void *tmp = ring->wp + ring->el_size;

drivers/bus/mhi/host/main.c

1193

buf_info = buf_ring->wp;

drivers/bus/mhi/host/main.c

1201

buf_info->wp = tre_ring->wp;

drivers/bus/mhi/host/main.c

1216

mhi_tre = tre_ring->wp;

drivers/bus/mhi/host/main.c

1276

cmd_tre = ring->wp;

drivers/bus/mhi/host/main.c

129

db = ring->iommu_base + (ring->wp - ring->base);

drivers/bus/mhi/host/main.c

140

db = ring->iommu_base + (ring->wp - ring->base);

drivers/bus/mhi/host/main.c

1521

while (tre_ring->rp != tre_ring->wp) {

drivers/bus/mhi/host/main.c

235

if (ring->wp < ring->rp) {

drivers/bus/mhi/host/main.c

236

nr_el = ((ring->rp - ring->wp) / ring->el_size) - 1;

drivers/bus/mhi/host/main.c

239

nr_el += ((ring->base + ring->len - ring->wp) /

drivers/bus/mhi/host/main.c

254

ring->wp += ring->el_size;

drivers/bus/mhi/host/main.c

255

if (ring->wp >= (ring->base + ring->len))

drivers/bus/mhi/host/main.c

256

ring->wp = ring->base;

drivers/bus/mhi/host/main.c

552

ring->wp += ring->el_size;

drivers/bus/mhi/host/main.c

554

if (ring->wp >= (ring->base + ring->len))

drivers/bus/mhi/host/main.c

555

ring->wp = ring->base;

drivers/bus/mhi/host/main.c

557

*ring->ctxt_wp = cpu_to_le64(ring->iommu_base + (ring->wp - ring->base));

drivers/bus/mhi/host/main.c

678

if (tre_ring->wp != tre_ring->rp &&

drivers/bus/mhi/host/pm.c

239

ring->wp = ring->base + ring->len - ring->el_size;

drivers/bus/mhi/host/pm.c

300

if (mhi_cmd->ring.rp != mhi_cmd->ring.wp)

drivers/bus/mhi/host/pm.c

319

if (tre_ring->base && tre_ring->wp != tre_ring->rp &&

drivers/bus/mhi/host/pm.c

443

ring->wp = ring->base + ring->len - ring->el_size;

drivers/bus/mhi/host/pm.c

559

ring->wp = ring->base;

drivers/bus/mhi/host/pm.c

561

cmd_ctxt->wp = cmd_ctxt->rbase;

drivers/bus/mhi/host/pm.c

575

ring->wp = ring->base;

drivers/bus/mhi/host/pm.c

577

er_ctxt->wp = er_ctxt->rbase;

drivers/bus/mhi/host/pm.c

716

ring->wp = ring->base;

drivers/bus/mhi/host/pm.c

718

cmd_ctxt->wp = cmd_ctxt->rbase;

drivers/bus/mhi/host/pm.c

732

ring->wp = ring->base;

drivers/bus/mhi/host/pm.c

734

er_ctxt->wp = er_ctxt->rbase;

drivers/bus/mhi/host/trace.h

100

__field(void *, wp)

drivers/bus/mhi/host/trace.h

109

__entry->wp = mhi_tre;

drivers/bus/mhi/host/trace.h

116

__get_str(name), __entry->ch_num, __entry->wp, __entry->tre_ptr,

drivers/clocksource/timer-ti-dm.c

169

u16 wp, offset;

drivers/clocksource/timer-ti-dm.c

171

wp = reg >> WPSHIFT;

drivers/clocksource/timer-ti-dm.c

175

if (wp && timer->posted)

drivers/clocksource/timer-ti-dm.c

176

while (readl_relaxed(timer->pend) & wp)

drivers/clocksource/timer-ti-dm.c

194

u16 wp, offset;

drivers/clocksource/timer-ti-dm.c

196

wp = reg >> WPSHIFT;

drivers/clocksource/timer-ti-dm.c

200

if (wp && timer->posted)

drivers/clocksource/timer-ti-dm.c

201

while (readl_relaxed(timer->pend) & wp)

drivers/dma/qcom/gpi.c

1122

gpi_write_ev_db(gpii, ev_ring, ev_ring->wp);

drivers/dma/qcom/gpi.c

1197

ch_ring->wp = ch_ring->base;

drivers/dma/qcom/gpi.c

1320

ring->wp = (ring->base + ring->len - ring->el_size);

drivers/dma/qcom/gpi.c

1329

gpi_write_ev_db(gpii, ring, ring->wp);

drivers/dma/qcom/gpi.c

1339

if (ring->wp < ring->rp) {

drivers/dma/qcom/gpi.c

1340

elements = ((ring->rp - ring->wp) / ring->el_size) - 1;

drivers/dma/qcom/gpi.c

1343

elements += ((ring->base + ring->len - ring->wp) / ring->el_size) - 1;

drivers/dma/qcom/gpi.c

1349

static int gpi_ring_add_element(struct gpi_ring *ring, void **wp)

drivers/dma/qcom/gpi.c

1354

*wp = ring->wp;

drivers/dma/qcom/gpi.c

1355

ring->wp += ring->el_size;

drivers/dma/qcom/gpi.c

1356

if (ring->wp >= (ring->base + ring->len))

drivers/dma/qcom/gpi.c

1357

ring->wp = ring->base;

drivers/dma/qcom/gpi.c

1368

ring->wp += ring->el_size;

drivers/dma/qcom/gpi.c

1369

if (ring->wp >= (ring->base + ring->len))

drivers/dma/qcom/gpi.c

1370

ring->wp = ring->base;

drivers/dma/qcom/gpi.c

1420

ring->wp = ring->base;

drivers/dma/qcom/gpi.c

1440

struct gpi_tre *gpi_tre, void **wp)

drivers/dma/qcom/gpi.c

1454

*wp = ch_tre;

drivers/dma/qcom/gpi.c

1871

void *tre, *wp = NULL;

drivers/dma/qcom/gpi.c

1892

gpi_queue_xfer(gpii, gchan, tre, &wp);

drivers/dma/qcom/gpi.c

1895

gpi_desc->db = ch_ring->wp;

drivers/dma/qcom/gpi.c

461

void *wp;

drivers/dma/qcom/gpi.c

538

static int gpi_ring_add_element(struct gpi_ring *ring, void **wp);

drivers/dma/qcom/gpi.c

718

struct gpi_ring *ring, void *wp)

drivers/dma/qcom/gpi.c

723

p_wp = to_physical(ring, wp);

drivers/dma/qcom/gpi.c

729

struct gpi_ring *ring, void *wp)

drivers/dma/qcom/gpi.c

733

p_wp = ring->phys_addr + (wp - ring->base);

drivers/gpu/drm/i915/display/skl_watermark.c

1660

u32 plane_pixel_rate, struct skl_wm_params *wp,

drivers/gpu/drm/i915/display/skl_watermark.c

1674

wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;

drivers/gpu/drm/i915/display/skl_watermark.c

1675

wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED &&

drivers/gpu/drm/i915/display/skl_watermark.c

1677

wp->rc_surface = intel_fb_is_ccs_modifier(modifier);

drivers/gpu/drm/i915/display/skl_watermark.c

1678

wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);

drivers/gpu/drm/i915/display/skl_watermark.c

1680

wp->width = width;

drivers/gpu/drm/i915/display/skl_watermark.c

1681

if (color_plane == 1 && wp->is_planar)

drivers/gpu/drm/i915/display/skl_watermark.c

1682

wp->width /= 2;

drivers/gpu/drm/i915/display/skl_watermark.c

1684

wp->cpp = format->cpp[color_plane];

drivers/gpu/drm/i915/display/skl_watermark.c

1685

wp->plane_pixel_rate = plane_pixel_rate;

drivers/gpu/drm/i915/display/skl_watermark.c

1688

modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)

drivers/gpu/drm/i915/display/skl_watermark.c

1689

wp->dbuf_block_size = 256;

drivers/gpu/drm/i915/display/skl_watermark.c

1691

wp->dbuf_block_size = 512;

drivers/gpu/drm/i915/display/skl_watermark.c

1694

switch (wp->cpp) {

drivers/gpu/drm/i915/display/skl_watermark.c

1696

wp->y_min_scanlines = 16;

drivers/gpu/drm/i915/display/skl_watermark.c

1699

wp->y_min_scanlines = 8;

drivers/gpu/drm/i915/display/skl_watermark.c

1702

wp->y_min_scanlines = 4;

drivers/gpu/drm/i915/display/skl_watermark.c

1705

MISSING_CASE(wp->cpp);

drivers/gpu/drm/i915/display/skl_watermark.c

1709

wp->y_min_scanlines = 4;

drivers/gpu/drm/i915/display/skl_watermark.c

1713

wp->y_min_scanlines *= 2;

drivers/gpu/drm/i915/display/skl_watermark.c

1715

wp->plane_bytes_per_line = wp->width * wp->cpp;

drivers/gpu/drm/i915/display/skl_watermark.c

1716

if (wp->y_tiled) {

drivers/gpu/drm/i915/display/skl_watermark.c

1717

interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *

drivers/gpu/drm/i915/display/skl_watermark.c

1718

wp->y_min_scanlines,

drivers/gpu/drm/i915/display/skl_watermark.c

1719

wp->dbuf_block_size);

drivers/gpu/drm/i915/display/skl_watermark.c

1726

wp->plane_blocks_per_line = div_fixed16(interm_pbpl,

drivers/gpu/drm/i915/display/skl_watermark.c

1727

wp->y_min_scanlines);

drivers/gpu/drm/i915/display/skl_watermark.c

1729

interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,

drivers/gpu/drm/i915/display/skl_watermark.c

1730

wp->dbuf_block_size);

drivers/gpu/drm/i915/display/skl_watermark.c

1732

if (!wp->x_tiled || DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_watermark.c

1735

wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);

drivers/gpu/drm/i915/display/skl_watermark.c

1738

wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,

drivers/gpu/drm/i915/display/skl_watermark.c

1739

wp->plane_blocks_per_line);

drivers/gpu/drm/i915/display/skl_watermark.c

1741

wp->linetime_us = skl_wm_linetime_us(crtc_state, plane_pixel_rate);

drivers/gpu/drm/i915/display/skl_watermark.c

1749

struct skl_wm_params *wp, int color_plane)

drivers/gpu/drm/i915/display/skl_watermark.c

1765

wp, color_plane,

drivers/gpu/drm/i915/display/skl_watermark.c

1797

const struct skl_wm_params *wp,

drivers/gpu/drm/i915/display/skl_watermark.c

1813

method1 = skl_wm_method1(display, wp->plane_pixel_rate,

drivers/gpu/drm/i915/display/skl_watermark.c

1814

wp->cpp, latency, wp->dbuf_block_size);

drivers/gpu/drm/i915/display/skl_watermark.c

1815

method2 = skl_wm_method2(wp->plane_pixel_rate,

drivers/gpu/drm/i915/display/skl_watermark.c

1818

wp->plane_blocks_per_line);

drivers/gpu/drm/i915/display/skl_watermark.c

1820

if (wp->y_tiled) {

drivers/gpu/drm/i915/display/skl_watermark.c

1821

selected_result = max_fixed16(method2, wp->y_tile_minimum);

drivers/gpu/drm/i915/display/skl_watermark.c

1825

if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /

drivers/gpu/drm/i915/display/skl_watermark.c

1826

wp->dbuf_block_size < 1) &&

drivers/gpu/drm/i915/display/skl_watermark.c

1827

(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {

drivers/gpu/drm/i915/display/skl_watermark.c

1829

} else if (latency >= wp->linetime_us) {

drivers/gpu/drm/i915/display/skl_watermark.c

1861

fixed16_to_u32_round_up(wp->plane_blocks_per_line));

drivers/gpu/drm/i915/display/skl_watermark.c

1863

wp->plane_blocks_per_line);

drivers/gpu/drm/i915/display/skl_watermark.c

1867

if (level == 0 && wp->rc_surface)

drivers/gpu/drm/i915/display/skl_watermark.c

1868

blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);

drivers/gpu/drm/i915/display/skl_watermark.c

1872

if (wp->y_tiled) {

drivers/gpu/drm/i915/display/skl_watermark.c

1873

blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);

drivers/gpu/drm/i915/display/skl_watermark.c

1874

lines += wp->y_min_scanlines;

drivers/gpu/drm/i915/display/skl_watermark.c

1894

if (wp->y_tiled) {

drivers/gpu/drm/i915/display/skl_watermark.c

1897

if (lines % wp->y_min_scanlines == 0)

drivers/gpu/drm/i915/display/skl_watermark.c

1898

extra_lines = wp->y_min_scanlines;

drivers/gpu/drm/i915/display/skl_watermark.c

1900

extra_lines = wp->y_min_scanlines * 2 -

drivers/gpu/drm/i915/display/skl_watermark.c

1901

lines % wp->y_min_scanlines;

drivers/gpu/drm/i915/display/skl_watermark.c

1904

wp->plane_blocks_per_line);

drivers/gpu/drm/i915/display/skl_watermark.c

1979

const struct skl_wm_params *wp)

drivers/gpu/drm/i915/display/skl_watermark.c

2020

if (wp->y_tiled) {

drivers/gpu/drm/i915/display/skl_watermark.c

2022

(u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);

drivers/gpu/drm/i915/display/skl_watermark.c

2168

struct skl_wm_params wp;

drivers/gpu/drm/i915/display/skl_watermark.c

2197

pixel_rate, &wp, 0, 1);

drivers/gpu/drm/i915/display/skl_watermark.c

2200

latency = skl_wm_latency(display, level, &wp);

drivers/gpu/drm/i915/display/skl_watermark.c

2202

skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);

drivers/gpu/drm/i915/display/skl_watermark.c

599

u32 plane_pixel_rate, struct skl_wm_params *wp,

drivers/gpu/drm/i915/display/skl_watermark.c

606

const struct skl_wm_params *wp,

drivers/gpu/drm/i915/display/skl_watermark.c

611

const struct skl_wm_params *wp)

drivers/gpu/drm/i915/display/skl_watermark.c

626

if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled)

drivers/gpu/drm/i915/display/skl_watermark.c

642

struct skl_wm_params wp;

drivers/gpu/drm/i915/display/skl_watermark.c

654

crtc_state->pixel_rate, &wp, 0, 0);

drivers/gpu/drm/i915/display/skl_watermark.c

658

unsigned int latency = skl_wm_latency(display, level, &wp);

drivers/gpu/drm/i915/display/skl_watermark.c

660

skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);

drivers/gpu/drm/omapdrm/dss/hdmi.h

239

struct hdmi_wp_data *wp;

drivers/gpu/drm/omapdrm/dss/hdmi.h

261

struct hdmi_wp_data *wp;

drivers/gpu/drm/omapdrm/dss/hdmi.h

296

int hdmi_wp_video_start(struct hdmi_wp_data *wp);

drivers/gpu/drm/omapdrm/dss/hdmi.h

297

void hdmi_wp_video_stop(struct hdmi_wp_data *wp);

drivers/gpu/drm/omapdrm/dss/hdmi.h

298

void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);

drivers/gpu/drm/omapdrm/dss/hdmi.h

299

u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);

drivers/gpu/drm/omapdrm/dss/hdmi.h

300

void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);

drivers/gpu/drm/omapdrm/dss/hdmi.h

301

void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);

drivers/gpu/drm/omapdrm/dss/hdmi.h

302

void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);

drivers/gpu/drm/omapdrm/dss/hdmi.h

303

int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);

drivers/gpu/drm/omapdrm/dss/hdmi.h

304

int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);

drivers/gpu/drm/omapdrm/dss/hdmi.h

305

void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi.h

307

void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi.h

309

void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi.h

313

int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi.h

315

phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);

drivers/gpu/drm/omapdrm/dss/hdmi.h

320

struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);

drivers/gpu/drm/omapdrm/dss/hdmi.h

337

int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);

drivers/gpu/drm/omapdrm/dss/hdmi.h

338

int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);

drivers/gpu/drm/omapdrm/dss/hdmi.h

339

void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi.h

341

void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi.h

356

struct hdmi_wp_data wp;

drivers/gpu/drm/omapdrm/dss/hdmi4.c

150

struct hdmi_wp_data *wp = &hdmi->wp;

drivers/gpu/drm/omapdrm/dss/hdmi4.c

159

hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

160

hdmi_wp_set_irqstatus(wp, ~HDMI_IRQ_CORE);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

196

r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

200

hdmi4_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

206

r = hdmi_wp_video_start(&hdmi->wp);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

210

hdmi_wp_set_irqenable(wp,

drivers/gpu/drm/omapdrm/dss/hdmi4.c

218

hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

230

hdmi_wp_clear_irqenable(&hdmi->wp, ~HDMI_IRQ_CORE);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

232

hdmi_wp_video_stop(&hdmi->wp);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

236

hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

254

hdmi_wp_dump(&hdmi->wp, s);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

266

hdmi_wp_audio_enable(&hd->wp, true);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

267

hdmi4_audio_start(&hd->core, &hd->wp);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

272

hdmi4_audio_stop(&hd->core, &hd->wp);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

273

hdmi_wp_audio_enable(&hd->wp, false);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

392

ret = hdmi4_audio_config(&hdmi->core, &hdmi->wp,

drivers/gpu/drm/omapdrm/dss/hdmi4.c

598

ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,

drivers/gpu/drm/omapdrm/dss/hdmi4.c

625

.audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),

drivers/gpu/drm/omapdrm/dss/hdmi4.c

655

r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

659

r = hdmi4_cec_init(hdmi->pdev, &hdmi->core, &hdmi->wp);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

67

struct hdmi_wp_data *wp = &hdmi->wp;

drivers/gpu/drm/omapdrm/dss/hdmi4.c

70

irqstatus = hdmi_wp_get_irqstatus(wp);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

71

hdmi_wp_set_irqstatus(wp, irqstatus);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

779

r = hdmi_wp_init(pdev, &hdmi->wp, 4);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

81

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

83

hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |

drivers/gpu/drm/omapdrm/dss/hdmi4.c

86

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

88

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

90

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

164

hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

165

hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

166

REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

178

REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

201

hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

238

REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

326

struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

337

core->wp = wp;

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c

340

REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h

20

struct hdmi_wp_data *wp);

drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h

33

struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

257

struct hdmi_wp_data *wp, struct hdmi_config *cfg)

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

270

hdmi_wp_video_config_timing(wp, &vm);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

275

hdmi_wp_video_config_format(wp, &video_format);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

277

hdmi_wp_video_config_interface(wp, &vm);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

632

int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

802

hdmi_wp_audio_config_dma(wp, &audio_dma);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

803

hdmi_wp_audio_config_format(wp, &audio_format);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

814

int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

819

hdmi_wp_audio_core_req_enable(wp, true);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

824

void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi4_core.c

829

hdmi_wp_audio_core_req_enable(wp, false);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.h

255

void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi4_core.h

264

int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.h

265

void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);

drivers/gpu/drm/omapdrm/dss/hdmi4_core.h

266

int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi5.c

104

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

106

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

172

hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

173

hdmi_wp_set_irqstatus(&hdmi->wp,

drivers/gpu/drm/omapdrm/dss/hdmi5.c

174

hdmi_wp_get_irqstatus(&hdmi->wp));

drivers/gpu/drm/omapdrm/dss/hdmi5.c

195

r = hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_LDOON);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

199

hdmi5_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

205

r = hdmi_wp_video_start(&hdmi->wp);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

209

hdmi_wp_set_irqenable(&hdmi->wp,

drivers/gpu/drm/omapdrm/dss/hdmi5.c

217

hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

229

hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

231

hdmi_wp_video_stop(&hdmi->wp);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

235

hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

253

hdmi_wp_dump(&hdmi->wp, s);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

265

REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

266

hdmi_wp_audio_enable(&hd->wp, true);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

267

hdmi_wp_audio_core_req_enable(&hd->wp, true);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

272

hdmi_wp_audio_core_req_enable(&hd->wp, false);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

273

hdmi_wp_audio_enable(&hd->wp, false);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

274

REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

390

ret = hdmi5_audio_config(&hdmi->core, &hdmi->wp,

drivers/gpu/drm/omapdrm/dss/hdmi5.c

449

idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

451

REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

459

REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

573

ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,

drivers/gpu/drm/omapdrm/dss/hdmi5.c

600

.audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),

drivers/gpu/drm/omapdrm/dss/hdmi5.c

613

REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

631

r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

68

struct hdmi_wp_data *wp = &hdmi->wp;

drivers/gpu/drm/omapdrm/dss/hdmi5.c

71

irqstatus = hdmi_wp_get_irqstatus(wp);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

72

hdmi_wp_set_irqstatus(wp, irqstatus);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

744

r = hdmi_wp_init(pdev, &hdmi->wp, 5);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

84

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

96

hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |

drivers/gpu/drm/omapdrm/dss/hdmi5.c

99

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

548

void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

572

hdmi_wp_video_config_timing(wp, &vm);

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

577

hdmi_wp_video_config_format(wp, &video_format);

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

579

hdmi_wp_video_config_interface(wp, &vm);

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

755

int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

844

hdmi_wp_audio_config_dma(wp, &audio_dma);

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

845

hdmi_wp_audio_config_format(wp, &audio_format);

drivers/gpu/drm/omapdrm/dss/hdmi5_core.h

289

void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi5_core.h

293

int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi_pll.c

147

if (hpll->wp->version == 4)

drivers/gpu/drm/omapdrm/dss/hdmi_pll.c

162

struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi_pll.c

167

pll->wp = wp;

drivers/gpu/drm/omapdrm/dss/hdmi_pll.c

42

struct hdmi_wp_data *wp = pll->wp;

drivers/gpu/drm/omapdrm/dss/hdmi_pll.c

50

r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);

drivers/gpu/drm/omapdrm/dss/hdmi_pll.c

60

struct hdmi_wp_data *wp = pll->wp;

drivers/gpu/drm/omapdrm/dss/hdmi_pll.c

63

hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

102

int hdmi_wp_video_start(struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

104

REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

109

void hdmi_wp_video_stop(struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

113

hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

115

REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

122

v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

130

void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

135

REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

140

hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

143

void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

153

r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

160

hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

163

void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

178

if (wp->version == 4)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

184

hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

189

hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

20

void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

22

#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

225

void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

232

r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

233

if (wp->version == 4) {

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

243

hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

246

void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

253

r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

256

hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

258

r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

261

hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

264

int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

266

REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

271

int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

273

REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

278

int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

284

wp->base = devm_ioremap_resource(&pdev->dev, res);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

285

if (IS_ERR(wp->base))

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

286

return PTR_ERR(wp->base);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

288

wp->phys_base = res->start;

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

289

wp->version = version;

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

294

phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

296

return wp->phys_base + HDMI_WP_AUDIO_DATA;

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

44

u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

46

return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

49

void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

51

hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

53

hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

56

void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

58

hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

61

void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

63

hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

67

int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

70

if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

74

REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

77

if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

87

int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

90

REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

93

if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)

drivers/hwmon/pmbus/pmbus_core.c

2728

switch (wp) {

drivers/hwmon/pmbus/pmbus_core.c

43

static int wp = -1;

drivers/hwmon/pmbus/pmbus_core.c

44

module_param(wp, int, 0444);

drivers/md/dm-zone.c

110

zone->wp = zone->start + zone->len;

drivers/md/dm-zone.c

112

zone->wp = zone->start;

drivers/md/dm-zone.c

114

zone->wp += sector_diff;

drivers/md/dm-zoned-metadata.c

1392

zone->wp_block = dmz_sect2blk(blkz->wp - blkz->start);

drivers/md/dm-zoned-metadata.c

1567

zone->wp_block = dmz_sect2blk(blkz->wp - blkz->start);

drivers/md/dm-zoned-metadata.c

1616

unsigned int wp = 0;

drivers/md/dm-zoned-metadata.c

1619

wp = zone->wp_block;

drivers/md/dm-zoned-metadata.c

1625

zone->id, zone->wp_block, wp);

drivers/md/dm-zoned-metadata.c

1627

if (zone->wp_block < wp) {

drivers/md/dm-zoned-metadata.c

1629

wp - zone->wp_block);

drivers/media/dvb-core/dvb_frontend.c

244

int wp;

drivers/media/dvb-core/dvb_frontend.c

253

wp = (events->eventw + 1) % MAX_EVENT;

drivers/media/dvb-core/dvb_frontend.c

254

if (wp == events->eventr) {

drivers/media/dvb-core/dvb_frontend.c

263

events->eventw = wp;

drivers/media/pci/saa7164/saa7164-core.c

355

u32 wp, mcb, rp;

drivers/media/pci/saa7164/saa7164-core.c

382

wp = saa7164_readl(port->bufcounter);

drivers/media/pci/saa7164/saa7164-core.c

383

if (wp > (port->hwcfg.buffercount - 1)) {

drivers/media/pci/saa7164/saa7164-core.c

384

printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp);

drivers/media/pci/saa7164/saa7164-core.c

389

if (wp == 0)

drivers/media/pci/saa7164/saa7164-core.c

392

mcb = wp - 1;

drivers/media/pci/saa7164/saa7164-core.c

431

u32 wp, mcb, rp;

drivers/media/pci/saa7164/saa7164-core.c

457

wp = saa7164_readl(port->bufcounter);

drivers/media/pci/saa7164/saa7164-core.c

458

if (wp > (port->hwcfg.buffercount - 1)) {

drivers/media/pci/saa7164/saa7164-core.c

459

printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp);

drivers/media/pci/saa7164/saa7164-core.c

464

if (wp == 0)

drivers/media/pci/saa7164/saa7164-core.c

467

mcb = wp - 1;

drivers/media/pci/saa7164/saa7164-core.c

572

int wp, i = 0, rp;

drivers/media/pci/saa7164/saa7164-core.c

575

wp = saa7164_readl(port->bufcounter);

drivers/media/pci/saa7164/saa7164-core.c

577

BUG_ON(wp > (port->hwcfg.buffercount - 1));

drivers/media/pci/saa7164/saa7164-core.c

580

if (wp == 0)

drivers/media/pci/saa7164/saa7164-core.c

583

rp = wp - 1;

drivers/media/pci/saa7164/saa7164-core.c

595

__func__, wp, rp);

drivers/media/test-drivers/vicodec/codec-fwht.c

122

s16 *wp = block;

drivers/media/test-drivers/vicodec/codec-fwht.c

151

*wp++ = 0;

drivers/media/test-drivers/vicodec/codec-fwht.c

156

*wp++ = 0;

drivers/media/test-drivers/vicodec/codec-fwht.c

157

*wp++ = coeff;

drivers/media/test-drivers/vicodec/codec-fwht.c

161

wp = block;

drivers/media/test-drivers/vicodec/codec-fwht.c

168

dwht_out[x + y * 8] = *wp++;

drivers/media/test-drivers/vicodec/codec-fwht.c

58

s16 *wp = block;

drivers/media/test-drivers/vicodec/codec-fwht.c

69

*wp = in[x + y * 8];

drivers/media/test-drivers/vicodec/codec-fwht.c

70

wp++;

drivers/mtd/maps/pcmciamtd.c

381

pr_debug("Region %d, wp = %u\n", i, t->dev[i].wp);

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1462

static void brcmnand_wp(struct mtd_info *mtd, int wp)

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1472

if (old_wp != wp) {

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1473

dev_dbg(ctrl->dev, "WP %s\n", str_on_off(wp));

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1474

old_wp = wp;

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1488

brcmnand_set_wp(ctrl, wp);

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1498

(wp ? 0 : NAND_STATUS_WP), 0);

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1503

str_on_off(wp));

drivers/mtd/nand/raw/nandsim.c

1619

if (ns->lines.wp) {

drivers/mtd/nand/raw/nandsim.c

1659

if (ns->lines.wp) {

drivers/mtd/nand/raw/nandsim.c

192

#define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))

drivers/mtd/nand/raw/nandsim.c

349

int wp; /* write Protect */

drivers/mtd/nand/raw/nandsim.c

886

struct weak_page *wp;

drivers/mtd/nand/raw/nandsim.c

905

wp = kzalloc_obj(*wp);

drivers/mtd/nand/raw/nandsim.c

906

if (!wp) {

drivers/mtd/nand/raw/nandsim.c

910

wp->page_no = page_no;

drivers/mtd/nand/raw/nandsim.c

911

wp->max_writes = max_writes;

drivers/mtd/nand/raw/nandsim.c

912

list_add(&wp->list, &weak_pages);

drivers/mtd/nand/raw/nandsim.c

919

struct weak_page *wp;

drivers/mtd/nand/raw/nandsim.c

921

list_for_each_entry(wp, &weak_pages, list)

drivers/mtd/nand/raw/nandsim.c

922

if (wp->page_no == page_no) {

drivers/mtd/nand/raw/nandsim.c

923

if (wp->writes_done >= wp->max_writes)

drivers/mtd/nand/raw/nandsim.c

925

wp->writes_done += 1;

drivers/net/ethernet/chelsio/cxgb3/sge.c

1116

struct work_request_hdr *wp = wrp;

drivers/net/ethernet/chelsio/cxgb3/sge.c

1156

wp->wr_lo = htonl(V_WR_LEN(WR_FLITS) | V_WR_GEN(ogen)) | wr_lo;

drivers/net/ethernet/chelsio/cxgb3/sge.c

1157

wr_gen2((struct tx_desc *)wp, ogen);

drivers/net/ethernet/smsc/smc91x.h

147

u16 *wp = (u16 *) p;

drivers/net/ethernet/smsc/smc91x.h

149

*wp++ = readw(a);

drivers/net/ethernet/smsc/smc91x.h

154

u16 *wp = (u16 *) p;

drivers/net/ethernet/smsc/smc91x.h

156

writew(*wp++, a);

drivers/net/hamradio/baycom_epp.c

361

unsigned char *wp, *bp;

drivers/net/hamradio/baycom_epp.c

374

wp = bc->hdlctx.buf;

drivers/net/hamradio/baycom_epp.c

379

*wp++ = 0x7e;

drivers/net/hamradio/baycom_epp.c

400

*wp++ = bitbuf;

drivers/net/hamradio/baycom_epp.c

408

*wp++ = bitbuf;

drivers/net/hamradio/baycom_epp.c

413

bc->hdlctx.bufcnt = wp - bc->hdlctx.buf;

drivers/net/wireless/realtek/rtlwifi/pci.h

275

static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size)

drivers/net/wireless/realtek/rtlwifi/pci.h

277

if (rp <= wp)

drivers/net/wireless/realtek/rtlwifi/pci.h

278

return size - 1 + rp - wp;

drivers/net/wireless/realtek/rtlwifi/pci.h

279

return rp - wp - 1;

drivers/net/wireless/realtek/rtw88/mac.c

1309

u32 wp, rp;

drivers/net/wireless/realtek/rtw88/mac.c

1342

wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;

drivers/net/wireless/realtek/rtw88/mac.c

1344

h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp;

drivers/net/wireless/realtek/rtw88/pci.c

1033

if (cur_wp >= ring->r.wp)

drivers/net/wireless/realtek/rtw88/pci.c

1034

count = cur_wp - ring->r.wp;

drivers/net/wireless/realtek/rtw88/pci.c

1036

count = ring->r.len - (ring->r.wp - cur_wp);

drivers/net/wireless/realtek/rtw88/pci.c

1113

ring->r.wp = cur_rp;

drivers/net/wireless/realtek/rtw88/pci.c

203

tx_ring->r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

293

rx_ring->r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

412

rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

420

rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

427

rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

434

rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

441

rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

448

rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

455

rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

462

rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

726

if (cur_rp == ring->r.wp)

drivers/net/wireless/realtek/rtw88/pci.c

785

rtw_write16(rtwdev, bd_idx, ring->r.wp & TRX_BD_IDX_MASK);

drivers/net/wireless/realtek/rtw88/pci.c

822

else if (!avail_desc(ring->r.wp, ring->r.rp, ring->r.len))

drivers/net/wireless/realtek/rtw88/pci.c

860

if (++ring->r.wp >= ring->r.len)

drivers/net/wireless/realtek/rtw88/pci.c

861

ring->r.wp = 0;

drivers/net/wireless/realtek/rtw88/pci.c

931

if (avail_desc(ring->r.wp, ring->r.rp, ring->r.len) < 2) {

drivers/net/wireless/realtek/rtw88/pci.c

983

avail_desc(ring->r.wp, rp_idx, ring->r.len) > 4) {

drivers/net/wireless/realtek/rtw88/pci.h

154

static inline int avail_desc(u32 wp, u32 rp, u32 len)

drivers/net/wireless/realtek/rtw88/pci.h

156

if (rp > wp)

drivers/net/wireless/realtek/rtw88/pci.h

157

return rp - wp - 1;

drivers/net/wireless/realtek/rtw88/pci.h

159

return len - wp + rp - 1;

drivers/net/wireless/realtek/rtw88/pci.h

183

u32 wp;

drivers/net/wireless/realtek/rtw88/pci.h

276

buf_desc = ring->r.head + ring->r.wp * size;

drivers/net/wireless/realtek/rtw89/core.c

2916

u8 wp, num = bcn_stat->num;

drivers/net/wireless/realtek/rtw89/core.c

2939

wp = bcn_stat->wp;

drivers/net/wireless/realtek/rtw89/core.c

2940

div_u64_rem(tsf - append, bcn_intvl_us, &bcn_stat->tbtt_us[wp]);

drivers/net/wireless/realtek/rtw89/core.c

2941

bcn_stat->tbtt_tu[wp] = bcn_stat->tbtt_us[wp] / 1024;

drivers/net/wireless/realtek/rtw89/core.c

2942

bcn_stat->wp = (wp + 1) % RTW89_BCN_TRACK_STAT_NR;

drivers/net/wireless/realtek/rtw89/core.h

5277

u8 wp;

drivers/net/wireless/realtek/rtw89/pci.c

1227

if (bd_ring->rp > bd_ring->wp)

drivers/net/wireless/realtek/rtw89/pci.c

1228

return bd_ring->rp - bd_ring->wp - 1;

drivers/net/wireless/realtek/rtw89/pci.c

1230

return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1;

drivers/net/wireless/realtek/rtw89/pci.c

1341

host_idx = bd_ring->wp;

drivers/net/wireless/realtek/rtw89/pci.c

1354

host_idx = bd_ring->wp + n_txbd;

drivers/net/wireless/realtek/rtw89/pci.c

1357

bd_ring->wp = host_idx;

drivers/net/wireless/realtek/rtw89/pci.c

1404

if (cur_rp == bd_ring->wp)

drivers/net/wireless/realtek/rtw89/pci.c

1804

bd_ring->wp = 0;

drivers/net/wireless/realtek/rtw89/pci.c

1839

bd_ring->wp = bd_ring->len - 1;

drivers/net/wireless/realtek/rtw89/pci.c

1841

bd_ring->wp = 0;

drivers/net/wireless/realtek/rtw89/pci.c

1865

rtw89_write16(rtwdev, addr_idx, bd_ring->wp);

drivers/net/wireless/realtek/rtw89/pci.c

310

u32 wp = bd_ring->wp;

drivers/net/wireless/realtek/rtw89/pci.c

313

return wp;

drivers/net/wireless/realtek/rtw89/pci.c

315

if (++wp >= bd_ring->len)

drivers/net/wireless/realtek/rtw89/pci.c

316

wp = 0;

drivers/net/wireless/realtek/rtw89/pci.c

318

return wp;

drivers/net/wireless/realtek/rtw89/pci.c

343

bd_ring->wp, ret);

drivers/net/wireless/realtek/rtw89/pci.c

3600

tx_ring->bd_ring.wp = 0;

drivers/net/wireless/realtek/rtw89/pci.c

3699

rx_ring->bd_ring.wp = len - 1;

drivers/net/wireless/realtek/rtw89/pci.c

3701

rx_ring->bd_ring.wp = 0;

drivers/net/wireless/realtek/rtw89/pci.c

433

rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp);

drivers/net/wireless/realtek/rtw89/pci.c

66

u32 cnt, cur_rp, wp, rp, len;

drivers/net/wireless/realtek/rtw89/pci.c

667

bd_ring->wp, ret);

drivers/net/wireless/realtek/rtw89/pci.c

69

wp = bd_ring->wp;

drivers/net/wireless/realtek/rtw89/pci.c

717

rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp);

drivers/net/wireless/realtek/rtw89/pci.c

77

wp += 1;

drivers/net/wireless/realtek/rtw89/pci.c

79

cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp);

drivers/net/wireless/realtek/rtw89/pci.h

1551

u32 wp; /* host idx */

drivers/net/wireless/realtek/rtw89/pci.h

1661

bd_ring->wp += cnt;

drivers/net/wireless/realtek/rtw89/pci.h

1663

if (bd_ring->wp >= bd_ring->len)

drivers/net/wireless/realtek/rtw89/pci.h

1664

bd_ring->wp -= bd_ring->len;

drivers/net/wireless/realtek/rtw89/pci.h

1685

tx_bd = head + bd_ring->wp;

drivers/nvme/host/zns.c

168

zone.wp = zone.start + zone.len;

drivers/nvme/host/zns.c

170

zone.wp = nvme_lba_to_sect(head, le64_to_cpu(entry->wp));

drivers/nvme/target/zns.c

233

zdesc.wp = nvmet_sect_to_lba(rz->req->ns, z->wp);

drivers/pcmcia/cistpl.c

674

device->dev[i].wp = (*p & 0x08) ? 1 : 0;

drivers/perf/arm-ccn.c

940

unsigned long wp = hw->config_base;

drivers/perf/arm-ccn.c

947

hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);

drivers/perf/arm-ccn.c

952

CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));

drivers/perf/arm-ccn.c

954

CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);

drivers/perf/arm-ccn.c

956

CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));

drivers/perf/arm-ccn.c

958

CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);

drivers/perf/arm-ccn.c

960

CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));

drivers/perf/arm-ccn.c

962

CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);

drivers/perf/arm-ccn.c

966

writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));

drivers/perf/arm-ccn.c

968

source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);

drivers/perf/arm-ccn.c

969

writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));

drivers/perf/arm-ccn.c

971

source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);

drivers/perf/arm-ccn.c

974

writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));

drivers/perf/arm-ccn.c

976

source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);

drivers/perf/arm-ccn.c

977

writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));

drivers/perf/arm-ccn.c

979

source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);

drivers/perf/arm-cmn.c

1633

u8 wp[CMN_MAX_DTMS][4];

drivers/perf/arm-cmn.c

1644

if (val->wp[dtm][wp_idx])

drivers/perf/arm-cmn.c

1645

if (val->wp[dtm][++wp_idx])

drivers/perf/arm-cmn.c

1683

val->wp[dtm][wp_idx] = 1;

drivers/pinctrl/renesas/pfc-r8a7778.c

1546

#define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp)

drivers/scsi/fcoe/fcoe_ctlr.c

1312

struct fip_wwn_desc *wp;

drivers/scsi/fcoe/fcoe_ctlr.c

1408

wp = (struct fip_wwn_desc *)desc;

drivers/scsi/fcoe/fcoe_ctlr.c

1409

if (dlen < sizeof(*wp))

drivers/scsi/fcoe/fcoe_ctlr.c

1411

if (get_unaligned_be64(&wp->fd_wwn) != fcf->switch_name)

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

868

int wp;

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

884

wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

886

hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1650

int wp;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1666

wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1668

hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1168

int wp;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1184

wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

1186

hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);

drivers/scsi/qedf/qedf_fip.c

174

struct fip_wwn_desc *wp;

drivers/scsi/qedf/qedf_fip.c

245

wp = (struct fip_wwn_desc *)desc;

drivers/scsi/qedf/qedf_fip.c

246

switch_name = get_unaligned_be64(&wp->fd_wwn);

drivers/scsi/scsi_debug.c

7408

module_param_named(wp, sdebug_wp, bool, S_IRUGO | S_IWUSR);

drivers/scsi/scsi_debug.c

7488

MODULE_PARM_DESC(wp, "Write Protect (def=0)");

drivers/scsi/sd_zbc.c

84

zone.wp = zone.start + zone.len;

drivers/scsi/sd_zbc.c

86

zone.wp = logical_to_sectors(sdp, get_unaligned_be64(&buf[24]));

drivers/staging/media/av7110/av7110_av.c

871

int wp;

drivers/staging/media/av7110/av7110_av.c

875

wp = (events->eventw + 1) % MAX_VIDEO_EVENT;

drivers/staging/media/av7110/av7110_av.c

876

if (wp == events->eventr) {

drivers/staging/media/av7110/av7110_av.c

883

events->eventw = wp;

drivers/target/target_core_fabric_configfs.c

184

unsigned long wp;

drivers/target/target_core_fabric_configfs.c

187

ret = kstrtoul(page, 0, &wp);

drivers/target/target_core_fabric_configfs.c

191

if ((wp != 1) && (wp != 0))

drivers/target/target_core_fabric_configfs.c

195

core_update_device_list_access(lacl->mapped_lun, wp, lacl->se_lun_nacl);

drivers/target/target_core_fabric_configfs.c

200

se_nacl->initiatorname, lacl->mapped_lun, (wp) ? "ON" : "OFF");

drivers/usb/gadget/udc/omap_udc.c

333

u16 *wp;

drivers/usb/gadget/udc/omap_udc.c

340

wp = (u16 *)buf;

drivers/usb/gadget/udc/omap_udc.c

342

omap_writew(*wp++, UDC_DATA);

drivers/usb/gadget/udc/omap_udc.c

345

buf = (u8 *)wp;

drivers/usb/gadget/udc/omap_udc.c

398

u16 *wp;

drivers/usb/gadget/udc/omap_udc.c

405

wp = (u16 *)buf;

drivers/usb/gadget/udc/omap_udc.c

407

*wp++ = omap_readw(UDC_DATA);

drivers/usb/gadget/udc/omap_udc.c

410

buf = (u8 *)wp;

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

233

struct hdmi_wp_data *wp;

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

277

int hdmi_wp_video_start(struct hdmi_wp_data *wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

278

void hdmi_wp_video_stop(struct hdmi_wp_data *wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

279

void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

280

u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

281

void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

282

void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

283

void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

284

int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

285

int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

286

void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

288

void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

290

void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

294

int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

295

phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

302

struct hdmi_wp_data *wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

318

int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

319

int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

320

void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

322

void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi.h

334

struct hdmi_wp_data wp;

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

148

struct hdmi_wp_data *wp = &hdmi.wp;

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

156

hdmi_wp_clear_irqenable(wp, 0xffffffff);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

157

hdmi_wp_set_irqstatus(wp, 0xffffffff);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

184

r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

188

hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

196

r = hdmi_wp_video_start(&hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

204

hdmi_wp_set_irqenable(wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

210

hdmi_wp_video_stop(&hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

212

hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

226

hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

230

hdmi_wp_video_stop(&hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

232

hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

277

hdmi_wp_dump(&hdmi.wp, s);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

305

hdmi_wp_audio_enable(&hd->wp, true);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

306

hdmi4_audio_start(&hd->core, &hd->wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

311

hdmi4_audio_stop(&hd->core, &hd->wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

312

hdmi_wp_audio_enable(&hd->wp, false);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

338

r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

61

struct hdmi_wp_data *wp = data;

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

630

ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

64

irqstatus = hdmi_wp_get_irqstatus(wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

65

hdmi_wp_set_irqstatus(wp, irqstatus);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

655

.audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

685

r = hdmi_wp_init(pdev, &hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

689

r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

710

IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

75

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

77

hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

80

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

82

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c

84

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

299

struct hdmi_wp_data *wp, struct hdmi_config *cfg)

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

312

hdmi_wp_video_config_timing(wp, &video_timing);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

317

hdmi_wp_video_config_format(wp, &video_format);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

319

hdmi_wp_video_config_interface(wp, &video_timing);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

676

int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

846

hdmi_wp_audio_config_dma(wp, &audio_dma);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

847

hdmi_wp_audio_config_format(wp, &audio_format);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

858

int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

863

hdmi_wp_audio_core_req_enable(wp, true);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

868

void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c

873

hdmi_wp_audio_core_req_enable(wp, false);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h

253

void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h

258

int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h

259

void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h

260

int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

101

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

103

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

178

hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

179

hdmi_wp_set_irqstatus(&hdmi.wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

180

hdmi_wp_get_irqstatus(&hdmi.wp));

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

201

r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

205

hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

213

r = hdmi_wp_video_start(&hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

221

hdmi_wp_set_irqenable(&hdmi.wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

227

hdmi_wp_video_stop(&hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

229

hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

243

hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

247

hdmi_wp_video_stop(&hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

249

hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

298

hdmi_wp_dump(&hdmi.wp, s);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

317

idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

319

REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

323

REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

333

REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

334

hdmi_wp_audio_enable(&hd->wp, true);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

335

hdmi_wp_audio_core_req_enable(&hd->wp, true);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

340

hdmi_wp_audio_core_req_enable(&hd->wp, false);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

341

hdmi_wp_audio_enable(&hd->wp, false);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

342

REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

368

r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

65

struct hdmi_wp_data *wp = data;

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

662

ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

68

irqstatus = hdmi_wp_get_irqstatus(wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

688

.audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

69

hdmi_wp_set_irqstatus(wp, irqstatus);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

701

REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

726

r = hdmi_wp_init(pdev, &hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

730

r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

751

IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

81

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

93

hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |

drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c

96

hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

570

void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

583

hdmi_wp_video_config_timing(wp, &video_timing);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

588

hdmi_wp_video_config_format(wp, &video_format);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

590

hdmi_wp_video_config_interface(wp, &video_timing);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

768

int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

857

hdmi_wp_audio_config_dma(wp, &audio_dma);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

858

hdmi_wp_audio_config_format(wp, &audio_format);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.h

286

void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.h

290

int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c

102

struct hdmi_wp_data *wp = pll->wp;

drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c

106

return hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c

112

struct hdmi_wp_data *wp = pll->wp;

drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c

114

hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c

209

struct hdmi_wp_data *wp)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c

213

pll->wp = wp;

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

103

int hdmi_wp_video_start(struct hdmi_wp_data *wp)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

105

REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

110

void hdmi_wp_video_stop(struct hdmi_wp_data *wp)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

114

hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

116

REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

123

v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

131

void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

136

REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

141

hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

144

void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

154

r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

159

hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

162

void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

173

hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

178

hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

203

void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

21

void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

210

r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

223

hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

226

void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

23

#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

233

r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

236

hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

238

r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

241

hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

244

int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

246

REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

251

int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

253

REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

258

int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

267

wp->phys_base = res->start;

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

269

wp->base = devm_ioremap_resource(&pdev->dev, res);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

270

if (IS_ERR(wp->base)) {

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

272

return PTR_ERR(wp->base);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

278

phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

280

return wp->phys_base + HDMI_WP_AUDIO_DATA;

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

45

u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

47

return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

50

void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

52

hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

54

hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

57

void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

59

hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

62

void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

64

hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

68

int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

71

if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

75

REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

78

if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

88

int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

91

REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);

drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c

94

if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)

fs/btrfs/zoned.c

1003

zone->wp = zone->start + zone->len;

fs/btrfs/zoned.c

1406

info->alloc_offset = ((zone.wp - zone.start) << SECTOR_SHIFT);

fs/btrfs/zoned.c

153

sector = zones[0].wp;

fs/btrfs/zoned.c

155

sector = zones[1].wp;

fs/btrfs/zoned.c

211

zones[i].wp = zones[i].start + zone_sectors;

fs/btrfs/zoned.c

215

if (zones[i].wp >= bdev_size) {

fs/btrfs/zoned.c

2347

u64 wp;

fs/btrfs/zoned.c

2357

wp = physical_start + ((zone.wp - zone.start) << SECTOR_SHIFT);

fs/btrfs/zoned.c

2359

if (physical_pos == wp)

fs/btrfs/zoned.c

2362

if (unlikely(physical_pos > wp))

fs/btrfs/zoned.c

2365

length = wp - physical_pos;

fs/btrfs/zoned.c

76

(zone->wp + SUPER_INFO_SECTORS > zone->start + zone->capacity);

fs/btrfs/zoned.c

817

u64 wp;

fs/btrfs/zoned.c

825

ret = sb_write_pointer(bdev, zones, &wp);

fs/btrfs/zoned.c

832

if (wp == zones[0].start << SECTOR_SHIFT)

fs/btrfs/zoned.c

834

else if (wp == zones[1].start << SECTOR_SHIFT)

fs/btrfs/zoned.c

850

reset->wp = reset->start;

fs/btrfs/zoned.c

859

if (wp == zones[0].start << SECTOR_SHIFT)

fs/btrfs/zoned.c

861

else if (wp == zones[1].start << SECTOR_SHIFT)

fs/btrfs/zoned.c

864

wp = ALIGN_DOWN(zone_end << SECTOR_SHIFT,

fs/btrfs/zoned.c

867

wp -= BTRFS_SUPER_INFO_SIZE;

fs/btrfs/zoned.c

870

*bytenr_ret = wp;

fs/btrfs/zoned.c

979

zone->wp += SUPER_INFO_SECTORS;

fs/btrfs/zoned.c

990

if (zone->wp != zone->start + zone->capacity) {

fs/f2fs/segment.c

5367

ret = blkdev_issue_zeroout(fdev->bdev, zone->wp,

fs/f2fs/segment.c

5368

zone->len - (zone->wp - zone->start),

fs/f2fs/segment.c

5441

wp_block = zbd->start_blk + (zone.wp >> log_sectors_per_block);

fs/f2fs/segment.c

5444

wp_sector_off = zone.wp & GENMASK(log_sectors_per_block - 1, 0);

fs/f2fs/segment.c

5492

if (zone.wp != zone.start) {

fs/xfs/libxfs/xfs_zones.c

32

if (zone->wp < zone->start ||

fs/xfs/libxfs/xfs_zones.c

33

zone->wp >= zone->start + zone->capacity) {

fs/xfs/libxfs/xfs_zones.c

36

zone_no, zone->wp);

fs/xfs/libxfs/xfs_zones.c

40

*write_pointer = XFS_BB_TO_FSB(mp, zone->wp - zone->start);

fs/zonefs/super.c

221

return (zone->wp - zone->start) << SECTOR_SHIFT;

fs/zonefs/super.c

384

zone.wp = zone.start + zone.len;

include/linux/nvme.h

817

__le64 wp;

include/linux/srcutiny.h

34

void srcu_drive_gp(struct work_struct *wp);

include/pcmcia/cistpl.h

107

u_char wp;

include/sound/hdaudio.h

272

unsigned short rp, wp; /* RIRB read/write pointers */

include/trace/events/rpcrdma.h

814

DEFINE_WRCH_EVENT(wp);

include/uapi/linux/blkzoned.h

132

__u64 wp; /* Zone write pointer position */

kernel/rcu/srcutiny.c

122

void srcu_drive_gp(struct work_struct *wp)

kernel/rcu/srcutiny.c

129

ssp = container_of(wp, struct srcu_struct, srcu_work);

kernel/rcu/tasks.h

222

static void rcu_tasks_invoke_cbs_wq(struct work_struct *wp);

kernel/rcu/tasks.h

585

static void rcu_tasks_invoke_cbs_wq(struct work_struct *wp)

kernel/rcu/tasks.h

588

struct rcu_tasks_percpu *rtpcp = container_of(wp, struct rcu_tasks_percpu, rtp_work);

kernel/rcu/tree.h

547

static void sync_rcu_do_polled_gp(struct work_struct *wp);

kernel/rcu/tree_exp.h

450

static void sync_rcu_exp_select_node_cpus(struct kthread_work *wp)

kernel/rcu/tree_exp.h

453

container_of(wp, struct rcu_exp_work, rew_work);

kernel/rcu/tree_exp.h

487

static void wait_rcu_exp_gp(struct kthread_work *wp)

kernel/rcu/tree_exp.h

491

rewp = container_of(wp, struct rcu_exp_work, rew_work);

kernel/rcu/tree_exp.h

988

static void sync_rcu_do_polled_gp(struct work_struct *wp)

kernel/rcu/tree_exp.h

992

struct rcu_node *rnp = container_of(wp, struct rcu_node, exp_poll_wq);

lib/crypto/mpi/generic_mpih-lshift.c

28

mpihelp_lshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned int cnt)

lib/crypto/mpi/generic_mpih-lshift.c

36

wp += 1;

lib/crypto/mpi/generic_mpih-lshift.c

44

wp[i] = (high_limb << sh_1) | (low_limb >> sh_2);

lib/crypto/mpi/generic_mpih-lshift.c

47

wp[i] = high_limb << sh_1;

lib/crypto/mpi/generic_mpih-rshift.c

29

mpihelp_rshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned cnt)

lib/crypto/mpi/generic_mpih-rshift.c

37

wp -= 1;

lib/crypto/mpi/generic_mpih-rshift.c

44

wp[i] = (low_limb >> sh_1) | (high_limb << sh_2);

lib/crypto/mpi/generic_mpih-rshift.c

47

wp[i] = low_limb >> sh_1;

lib/crypto/mpi/mpi-add.c

20

mpi_ptr_t wp, up, vp;

lib/crypto/mpi/mpi-add.c

50

wp = w->d;

lib/crypto/mpi/mpi-add.c

54

MPN_COPY(wp, up, usize);

lib/crypto/mpi/mpi-add.c

60

mpihelp_sub(wp, up, usize, vp, vsize);

lib/crypto/mpi/mpi-add.c

62

MPN_NORMALIZE(wp, wsize);

lib/crypto/mpi/mpi-add.c

65

mpihelp_sub_n(wp, vp, up, usize);

lib/crypto/mpi/mpi-add.c

67

MPN_NORMALIZE(wp, wsize);

lib/crypto/mpi/mpi-add.c

71

mpihelp_sub_n(wp, up, vp, usize);

lib/crypto/mpi/mpi-add.c

73

MPN_NORMALIZE(wp, wsize);

lib/crypto/mpi/mpi-add.c

78

mpi_limb_t cy = mpihelp_add(wp, up, usize, vp, vsize);

lib/crypto/mpi/mpi-add.c

79

wp[usize] = cy;

lib/crypto/mpi/mpi-internal.h

198

mpi_limb_t mpihelp_lshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize,

lib/crypto/mpi/mpi-internal.h

200

mpi_limb_t mpihelp_rshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize,

lib/crypto/mpi/mpi-mul.c

21

mpi_ptr_t up, vp, wp;

lib/crypto/mpi/mpi-mul.c

45

wp = w->d;

lib/crypto/mpi/mpi-mul.c

50

if (wp == up || wp == vp) {

lib/crypto/mpi/mpi-mul.c

51

wp = mpi_alloc_limb_space(wsize);

lib/crypto/mpi/mpi-mul.c

52

if (!wp)

lib/crypto/mpi/mpi-mul.c

59

wp = w->d;

lib/crypto/mpi/mpi-mul.c

62

if (wp == up) {

lib/crypto/mpi/mpi-mul.c

68

if (wp == vp)

lib/crypto/mpi/mpi-mul.c

71

MPN_COPY(up, wp, usize);

lib/crypto/mpi/mpi-mul.c

72

} else if (wp == vp) {

lib/crypto/mpi/mpi-mul.c

78

MPN_COPY(vp, wp, vsize);

lib/crypto/mpi/mpi-mul.c

85

err = mpihelp_mul(wp, up, usize, vp, vsize, &cy);

lib/crypto/mpi/mpi-mul.c

88

mpi_free_limb_space(wp);

lib/crypto/mpi/mpi-mul.c

95

mpi_assign_limb_space(w, wp, wsize);

lib/inflate.c

1093

wp = 0;

lib/inflate.c

1121

flush_output(wp);

lib/inflate.c

171

#define flush_output(w) (wp=(w),flush_window())

lib/inflate.c

610

w = wp; /* initialize window position */

lib/inflate.c

691

wp = w; /* restore global window pointer */

lib/inflate.c

717

w = wp; /* initialize window position */

lib/inflate.c

750

wp = w; /* restore global window pointer */

sound/hda/core/bus.c

147

unsigned int wp;

sound/hda/core/bus.c

153

wp = (bus->unsol_wp + 1) % HDA_UNSOL_QUEUE_SIZE;

sound/hda/core/bus.c

154

bus->unsol_wp = wp;

sound/hda/core/bus.c

156

wp <<= 1;

sound/hda/core/bus.c

157

bus->unsol_queue[wp] = res;

sound/hda/core/bus.c

158

bus->unsol_queue[wp + 1] = res_ex;

sound/hda/core/controller.c

222

unsigned int wp, rp;

sound/hda/core/controller.c

229

wp = snd_hdac_chip_readw(bus, CORBWP);

sound/hda/core/controller.c

230

if (wp == 0xffff) {

sound/hda/core/controller.c

234

wp++;

sound/hda/core/controller.c

235

wp %= AZX_MAX_CORB_ENTRIES;

sound/hda/core/controller.c

238

if (wp == rp) {

sound/hda/core/controller.c

244

bus->corb.buf[wp] = cpu_to_le32(val);

sound/hda/core/controller.c

245

snd_hdac_chip_writew(bus, CORBWP, wp);

sound/hda/core/controller.c

261

unsigned int rp, wp;

sound/hda/core/controller.c

265

wp = snd_hdac_chip_readw(bus, RIRBWP);

sound/hda/core/controller.c

266

if (wp == 0xffff) {

sound/hda/core/controller.c

271

if (wp == bus->rirb.wp)

sound/hda/core/controller.c

273

bus->rirb.wp = wp;

sound/hda/core/controller.c

275

while (bus->rirb.rp != wp) {

sound/hda/core/controller.c

286

res, res_ex, bus->rirb.rp, wp);

sound/hda/core/controller.c

71

bus->rirb.wp = bus->rirb.rp = 0;

sound/pci/lola/lola.c

109

unsigned int rp, wp;

sound/pci/lola/lola.c

112

wp = lola_readw(chip, BAR0, RIRBWP);

sound/pci/lola/lola.c

113

if (wp == chip->rirb.wp)

sound/pci/lola/lola.c

115

chip->rirb.wp = wp;

sound/pci/lola/lola.c

117

while (chip->rirb.rp != wp) {

sound/pci/lola/lola.c

385

chip->corb.wp = 0;

sound/pci/lola/lola.c

87

unsigned int wp = chip->corb.wp + 1;

sound/pci/lola/lola.c

88

wp %= LOLA_CORB_ENTRIES;

sound/pci/lola/lola.c

89

chip->corb.wp = wp;

sound/pci/lola/lola.c

90

chip->corb.buf[wp * 2] = cpu_to_le32(data);

sound/pci/lola/lola.c

91

chip->corb.buf[wp * 2 + 1] = cpu_to_le32(extdata);

sound/pci/lola/lola.c

92

lola_writew(chip, BAR0, CORBWP, wp);

sound/pci/lola/lola.h

212

unsigned short rp, wp; /* read/write pointers */

tools/perf/tests/tests.h

126

DECLARE_SUITE(wp);

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

112

static bool run_test(int wr_size, int wp_size, int wr, int wp)

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

143

if (!set_watchpoint(pid, wp_size, wp))

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

204

int wr, wp, size;

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

216

for (wp = wr - size; wp <= wr + size; wp = wp + size) {

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

217

result = run_test(size, MIN(size, 8), wr, wp);

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

218

if ((result && wr == wp) ||

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

219

(!result && wr != wp))

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

222

size, wr, wp);

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

226

size, wr, wp);

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

81

static bool set_watchpoint(pid_t pid, int size, int wp)

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

83

const volatile uint8_t *addr = &var[32 + wp];

tools/testing/selftests/mm/pagemap_ioctl.c

119

struct uffdio_writeprotect wp;

tools/testing/selftests/mm/pagemap_ioctl.c

130

wp.range.start = (unsigned long)lpBaseAddress;

tools/testing/selftests/mm/pagemap_ioctl.c

131

wp.range.len = dwRegionSize;

tools/testing/selftests/mm/pagemap_ioctl.c

132

wp.mode = UFFDIO_WRITEPROTECT_MODE_WP;

tools/testing/selftests/mm/pagemap_ioctl.c

134

if (ioctl(uffd, UFFDIO_WRITEPROTECT, &wp))

tools/testing/selftests/mm/uffd-common.c

402

void wp_range(int ufd, __u64 start, __u64 len, bool wp)

tools/testing/selftests/mm/uffd-common.c

410

prms.mode = wp ? UFFDIO_WRITEPROTECT_MODE_WP : 0;

tools/testing/selftests/mm/uffd-common.c

416

static void continue_range(int ufd, __u64 start, __u64 len, bool wp)

tools/testing/selftests/mm/uffd-common.c

424

if (wp)

tools/testing/selftests/mm/uffd-common.c

627

int __copy_page(uffd_global_test_opts_t *gopts, unsigned long offset, bool retry, bool wp)

tools/testing/selftests/mm/uffd-common.c

636

if (wp)

tools/testing/selftests/mm/uffd-common.c

659

int copy_page(uffd_global_test_opts_t *gopts, unsigned long offset, bool wp)

tools/testing/selftests/mm/uffd-common.c

661

return __copy_page(gopts, offset, false, wp);

tools/testing/selftests/mm/uffd-common.h

121

void wp_range(int ufd, __u64 start, __u64 len, bool wp);

tools/testing/selftests/mm/uffd-common.h

125

int __copy_page(uffd_global_test_opts_t *gopts, unsigned long offset, bool retry, bool wp);

tools/testing/selftests/mm/uffd-common.h

126

int copy_page(uffd_global_test_opts_t *gopts, unsigned long offset, bool wp);

tools/testing/selftests/mm/uffd-unit-tests.c

1466

bool wp,

tools/testing/selftests/mm/uffd-unit-tests.c

1474

miss, wp, minor, &ioctls);

tools/testing/selftests/mm/uffd-unit-tests.c

1484

(!miss && !wp && !minor)) {

tools/testing/selftests/mm/uffd-unit-tests.c

1487

"with wrong errno=%d", miss, wp, minor, ret);

tools/testing/selftests/mm/uffd-unit-tests.c

1494

if (wp)

tools/testing/selftests/mm/uffd-unit-tests.c

1502

"returned=0x%"PRIx64, miss, wp, minor, expected, ioctls);

tools/testing/selftests/mm/uffd-unit-tests.c

1510

int miss, wp, minor;

tools/testing/selftests/mm/uffd-unit-tests.c

1513

for (wp = 0; wp <= 1; wp++)

tools/testing/selftests/mm/uffd-unit-tests.c

1515

do_register_ioctls_test(gopts, args, miss, wp, minor);

tools/testing/selftests/mm/uffd-unit-tests.c

207

#define pagemap_check_wp(value, wp) do { \

tools/testing/selftests/mm/uffd-unit-tests.c

208

if (!!(value & PM_UFFD_WP) != wp) \

tools/testing/selftests/mm/uffd-unit-tests.c

658

static int faulting_process(uffd_global_test_opts_t *gopts, int signal_test, bool wp)

tools/testing/selftests/mm/uffd-unit-tests.c

693

if (copy_page(gopts, offset, wp))

tools/testing/selftests/mm/uffd-unit-tests.c

756

static void uffd_sigbus_test_common(uffd_global_test_opts_t *gopts, bool wp)

tools/testing/selftests/mm/uffd-unit-tests.c

771

true, wp, false))

tools/testing/selftests/mm/uffd-unit-tests.c

774

if (faulting_process(gopts, 1, wp))

tools/testing/selftests/mm/uffd-unit-tests.c

779

args.apply_wp = wp;

tools/testing/selftests/mm/uffd-unit-tests.c

791

exit(faulting_process(gopts, 2, wp));

tools/testing/selftests/mm/uffd-unit-tests.c

817

static void uffd_events_test_common(uffd_global_test_opts_t *gopts, bool wp)

tools/testing/selftests/mm/uffd-unit-tests.c

830

true, wp, false))

tools/testing/selftests/mm/uffd-unit-tests.c

833

args.apply_wp = wp;

tools/testing/selftests/mm/uffd-unit-tests.c

845

exit(faulting_process(gopts, 0, wp));

tools/testing/selftests/mm/vm_util.c

356

bool miss, bool wp, bool minor, uint64_t *ioctls)

tools/testing/selftests/mm/vm_util.c

364

if (wp)

tools/testing/selftests/mm/vm_util.c

382

bool miss, bool wp, bool minor)

tools/testing/selftests/mm/vm_util.c

385

miss, wp, minor, NULL);

tools/testing/selftests/mm/vm_util.h

102

bool miss, bool wp, bool minor);

tools/testing/selftests/mm/vm_util.h

105

bool miss, bool wp, bool minor, uint64_t *ioctls);

tools/testing/selftests/powerpc/nx-gzip/gunz_test.c

315

char *wp;

tools/testing/selftests/powerpc/nx-gzip/gunz_test.c

324

wp = (NULL != (wp = strrchr(argv[1], '/'))) ? (wp+1) : argv[1];

tools/testing/selftests/powerpc/nx-gzip/gunz_test.c

325

strcpy(w, wp);