arch/s390/kernel/traps.c

179

int si_code, vic;

arch/s390/kernel/traps.c

183

vic = (current->thread.ufpu.fpc & 0xf00) >> 8;

arch/s390/kernel/traps.c

184

switch (vic) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6743

timing_out->vic = old_stream->timing.vic;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6747

timing_out->vic = drm_match_cea_mode(mode_in);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6761

timing_out->vic = avi_frame.video_code;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6768

timing_out->hdmi_vic = hv_frame.vic;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4503

unsigned int vic = pipe_ctx->stream->timing.vic;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4659

vic = 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4666

vic = 95;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4669

vic = 94;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4672

vic = 93;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4675

vic = 98;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4682

hdmi_info.bits.VIC0_VIC7 = vic;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4683

if (vic >= 128)

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

985

uint32_t vic;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

147

timing->vic == 0 && timing->hdmi_vic == 0 &&

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

1307

int vic;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

1315

vic = drm_match_cea_mode(mode);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

1316

if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

1317

(vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

1320

} else if (vic) {

drivers/gpu/drm/bridge/inno-hdmi.c

637

u8 vic = drm_match_cea_mode(mode);

drivers/gpu/drm/bridge/inno-hdmi.c

639

if (vic == 6 || vic == 7 || vic == 21 || vic == 22 ||

drivers/gpu/drm/bridge/inno-hdmi.c

640

vic == 2 || vic == 3 || vic == 17 || vic == 18)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1227

u8 init_threshold, vic;

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1273

vic = drm_match_cea_mode(mode);

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1274

if (vic == 5 || vic == 6 || vic == 7 ||

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1275

vic == 10 || vic == 11 || vic == 20 ||

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1276

vic == 21 || vic == 22 || vic == 39 ||

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1277

vic == 25 || vic == 26 || vic == 40 ||

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1278

vic == 44 || vic == 45 || vic == 46 ||

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1279

vic == 50 || vic == 51 || vic == 54 ||

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1280

vic == 55 || vic == 58 || vic == 59)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

146

int vic;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2050

if (hdmi->vic == 39)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2262

hdmi->vic = drm_match_cea_mode(mode);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2264

if (!hdmi->vic) {

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2267

dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2270

if ((hdmi->vic == 6) || (hdmi->vic == 7) ||

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2271

(hdmi->vic == 21) || (hdmi->vic == 22) ||

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2272

(hdmi->vic == 2) || (hdmi->vic == 3) ||

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2273

(hdmi->vic == 17) || (hdmi->vic == 18))

drivers/gpu/drm/display/drm_dp_helper.c

1609

u8 vic;

drivers/gpu/drm/display/drm_dp_helper.c

1621

vic = 6;

drivers/gpu/drm/display/drm_dp_helper.c

1624

vic = 21;

drivers/gpu/drm/display/drm_dp_helper.c

1627

vic = 5;

drivers/gpu/drm/display/drm_dp_helper.c

1630

vic = 20;

drivers/gpu/drm/display/drm_dp_helper.c

1633

vic = 4;

drivers/gpu/drm/display/drm_dp_helper.c

1636

vic = 19;

drivers/gpu/drm/display/drm_dp_helper.c

1641

return drm_display_mode_from_cea_vic(dev, vic);

drivers/gpu/drm/display/drm_hdmi_helper.c

216

unsigned int vic = drm_match_cea_mode(mode);

drivers/gpu/drm/display/drm_hdmi_helper.c

222

if (vic == 1 && bpc != 8)

drivers/gpu/drm/display/drm_hdmi_state_helper.c

385

u8 vic = drm_match_cea_mode(mode);

drivers/gpu/drm/display/drm_hdmi_state_helper.c

397

if (vic == 1 && bpc != 8) {

drivers/gpu/drm/drm_edid.c

4239

static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)

drivers/gpu/drm/drm_edid.c

4244

if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))

drivers/gpu/drm/drm_edid.c

4245

return &edid_cea_modes_1[vic - 1];

drivers/gpu/drm/drm_edid.c

4246

if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))

drivers/gpu/drm/drm_edid.c

4247

return &edid_cea_modes_193[vic - 193];

drivers/gpu/drm/drm_edid.c

4256

static u8 cea_next_vic(u8 vic)

drivers/gpu/drm/drm_edid.c

4258

if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))

drivers/gpu/drm/drm_edid.c

4259

vic = 193;

drivers/gpu/drm/drm_edid.c

4260

return vic;

drivers/gpu/drm/drm_edid.c

4289

cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)

drivers/gpu/drm/drm_edid.c

4309

if (((vic == 8 || vic == 9 ||

drivers/gpu/drm/drm_edid.c

4310

vic == 12 || vic == 13) && mode->vtotal < 263) ||

drivers/gpu/drm/drm_edid.c

4311

((vic == 23 || vic == 24 ||

drivers/gpu/drm/drm_edid.c

4312

vic == 27 || vic == 28) && mode->vtotal < 314)) {

drivers/gpu/drm/drm_edid.c

4327

u8 vic;

drivers/gpu/drm/drm_edid.c

4335

for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {

drivers/gpu/drm/drm_edid.c

4339

drm_mode_init(&cea_mode, cea_mode_for_vic(vic));

drivers/gpu/drm/drm_edid.c

4351

return vic;

drivers/gpu/drm/drm_edid.c

4352

} while (cea_mode_alternate_timings(vic, &cea_mode));

drivers/gpu/drm/drm_edid.c

4368

u8 vic;

drivers/gpu/drm/drm_edid.c

4376

for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {

drivers/gpu/drm/drm_edid.c

4380

drm_mode_init(&cea_mode, cea_mode_for_vic(vic));

drivers/gpu/drm/drm_edid.c

4392

return vic;

drivers/gpu/drm/drm_edid.c

4393

} while (cea_mode_alternate_timings(vic, &cea_mode));

drivers/gpu/drm/drm_edid.c

4400

static bool drm_valid_cea_vic(u8 vic)

drivers/gpu/drm/drm_edid.c

4402

return cea_mode_for_vic(vic) != NULL;

drivers/gpu/drm/drm_edid.c

4434

u8 vic;

drivers/gpu/drm/drm_edid.c

4442

for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {

drivers/gpu/drm/drm_edid.c

4443

const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];

drivers/gpu/drm/drm_edid.c

4455

return vic;

drivers/gpu/drm/drm_edid.c

4472

u8 vic;

drivers/gpu/drm/drm_edid.c

4480

for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {

drivers/gpu/drm/drm_edid.c

4481

const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];

drivers/gpu/drm/drm_edid.c

4491

return vic;

drivers/gpu/drm/drm_edid.c

4496

static bool drm_valid_hdmi_vic(u8 vic)

drivers/gpu/drm/drm_edid.c

4498

return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);

drivers/gpu/drm/drm_edid.c

4520

u8 vic = drm_match_cea_mode(mode);

drivers/gpu/drm/drm_edid.c

4523

if (drm_valid_cea_vic(vic)) {

drivers/gpu/drm/drm_edid.c

4524

cea_mode = cea_mode_for_vic(vic);

drivers/gpu/drm/drm_edid.c

4527

vic = drm_match_hdmi_mode(mode);

drivers/gpu/drm/drm_edid.c

4528

if (drm_valid_hdmi_vic(vic)) {

drivers/gpu/drm/drm_edid.c

4529

cea_mode = &edid_4k_modes[vic];

drivers/gpu/drm/drm_edid.c

4615

u8 vic = svd_to_vic(svds[i]);

drivers/gpu/drm/drm_edid.c

4618

if (!drm_valid_cea_vic(vic))

drivers/gpu/drm/drm_edid.c

4621

newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));

drivers/gpu/drm/drm_edid.c

4745

static int add_hdmi_mode(struct drm_connector *connector, u8 vic)

drivers/gpu/drm/drm_edid.c

4750

if (!drm_valid_hdmi_vic(vic)) {

drivers/gpu/drm/drm_edid.c

4752

connector->base.id, connector->name, vic);

drivers/gpu/drm/drm_edid.c

4756

newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);

drivers/gpu/drm/drm_edid.c

4864

u8 vic;

drivers/gpu/drm/drm_edid.c

4866

vic = db[9 + offset + i];

drivers/gpu/drm/drm_edid.c

4867

modes += add_hdmi_mode(connector, vic);

drivers/gpu/drm/drm_edid.c

5357

u8 vic;

drivers/gpu/drm/drm_edid.c

5364

vic = drm_match_cea_mode_clock_tolerance(mode, 5);

drivers/gpu/drm/drm_edid.c

5365

if (drm_valid_cea_vic(vic)) {

drivers/gpu/drm/drm_edid.c

5367

cea_mode = cea_mode_for_vic(vic);

drivers/gpu/drm/drm_edid.c

5371

vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);

drivers/gpu/drm/drm_edid.c

5372

if (drm_valid_hdmi_vic(vic)) {

drivers/gpu/drm/drm_edid.c

5374

cea_mode = &edid_4k_modes[vic];

drivers/gpu/drm/drm_edid.c

5394

type, vic, mode->clock, clock);

drivers/gpu/drm/drm_edid.c

6034

u8 vic = svd_to_vic(svds[i]);

drivers/gpu/drm/drm_edid.c

6036

if (!drm_valid_cea_vic(vic))

drivers/gpu/drm/drm_edid.c

6037

vic = 0;

drivers/gpu/drm/drm_edid.c

6039

info->vics[vic_index++] = vic;

drivers/gpu/drm/drm_edid.c

6056

u8 vic = info->vics[i];

drivers/gpu/drm/drm_edid.c

6058

if (vic && y420cmdb_map & BIT_ULL(i))

drivers/gpu/drm/drm_edid.c

6059

bitmap_set(hdmi->y420_cmdb_modes, vic, 1);

drivers/gpu/drm/drm_edid.c

6063

static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)

drivers/gpu/drm/drm_edid.c

6068

if (!vic || !info->vics)

drivers/gpu/drm/drm_edid.c

6072

if (info->vics[i] == vic)

drivers/gpu/drm/drm_edid.c

6089

u8 vic = svd_to_vic(svds[i]);

drivers/gpu/drm/drm_edid.c

6091

if (!drm_valid_cea_vic(vic))

drivers/gpu/drm/drm_edid.c

6094

bitmap_set(hdmi->y420_vdb_modes, vic, 1);

drivers/gpu/drm/drm_edid.c

7276

static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)

drivers/gpu/drm/drm_edid.c

7278

if (!is_hdmi2_sink(connector) && vic > 64 &&

drivers/gpu/drm/drm_edid.c

7279

!cta_vdb_has_vic(connector, vic))

drivers/gpu/drm/drm_edid.c

7282

return vic;

drivers/gpu/drm/drm_edid.c

7300

u8 vic, hdmi_vic;

drivers/gpu/drm/drm_edid.c

7310

vic = drm_mode_cea_vic(connector, mode);

drivers/gpu/drm/drm_edid.c

7329

if (vic)

drivers/gpu/drm/drm_edid.c

7330

picture_aspect = drm_get_cea_aspect_ratio(vic);

drivers/gpu/drm/drm_edid.c

7341

if (vic) {

drivers/gpu/drm/drm_edid.c

7342

if (picture_aspect != drm_get_cea_aspect_ratio(vic))

drivers/gpu/drm/drm_edid.c

7354

frame->video_code = vic_for_avi_infoframe(connector, vic);

drivers/gpu/drm/drm_edid.c

7490

frame->vic = drm_mode_hdmi_vic(connector, mode);

drivers/gpu/drm/drm_modes.c

2714

u8 vic = drm_match_cea_mode(mode);

drivers/gpu/drm/drm_modes.c

2716

return test_bit(vic, display->hdmi.y420_vdb_modes);

drivers/gpu/drm/drm_modes.c

2734

u8 vic = drm_match_cea_mode(mode);

drivers/gpu/drm/drm_modes.c

2736

return test_bit(vic, display->hdmi.y420_cmdb_modes);

drivers/gpu/drm/meson/meson_encoder_hdmi.c

101

if (meson_venc_hdmi_venc_repeat(vic) ||

drivers/gpu/drm/meson/meson_encoder_hdmi.c

131

int vic = drm_match_cea_mode(mode);

drivers/gpu/drm/meson/meson_encoder_hdmi.c

144

if (!vic) {

drivers/gpu/drm/meson/meson_encoder_hdmi.c

151

} else if (!meson_venc_hdmi_supported_vic(vic))

drivers/gpu/drm/meson/meson_encoder_hdmi.c

173

if (meson_venc_hdmi_venc_repeat(vic) ||

drivers/gpu/drm/meson/meson_encoder_hdmi.c

202

int vic;

drivers/gpu/drm/meson/meson_encoder_hdmi.c

218

vic = drm_match_cea_mode(mode);

drivers/gpu/drm/meson/meson_encoder_hdmi.c

220

dev_dbg(priv->dev, "\"%s\" vic %d\n", mode->name, vic);

drivers/gpu/drm/meson/meson_encoder_hdmi.c

229

meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode);

drivers/gpu/drm/meson/meson_encoder_hdmi.c

72

int vic = drm_match_cea_mode(mode);

drivers/gpu/drm/meson/meson_encoder_hdmi.c

87

if (!vic) {

drivers/gpu/drm/meson/meson_venc.c

1007

if (meson_venc_hdmi_venc_repeat(vic))

drivers/gpu/drm/meson/meson_venc.c

820

unsigned int vic;

drivers/gpu/drm/meson/meson_venc.c

881

bool meson_venc_hdmi_supported_vic(int vic)

drivers/gpu/drm/meson/meson_venc.c

885

while (vmode->vic && vmode->mode) {

drivers/gpu/drm/meson/meson_venc.c

886

if (vmode->vic == vic)

drivers/gpu/drm/meson/meson_venc.c

920

static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)

drivers/gpu/drm/meson/meson_venc.c

924

while (vmode->vic && vmode->mode) {

drivers/gpu/drm/meson/meson_venc.c

925

if (vmode->vic == vic)

drivers/gpu/drm/meson/meson_venc.c

933

bool meson_venc_hdmi_venc_repeat(int vic)

drivers/gpu/drm/meson/meson_venc.c

936

if (vic == 6 || vic == 7 || /* 480i */

drivers/gpu/drm/meson/meson_venc.c

937

vic == 21 || vic == 22 || /* 576i */

drivers/gpu/drm/meson/meson_venc.c

938

vic == 17 || vic == 18 || /* 576p */

drivers/gpu/drm/meson/meson_venc.c

939

vic == 2 || vic == 3 || /* 480p */

drivers/gpu/drm/meson/meson_venc.c

940

vic == 4 || /* 720p60 */

drivers/gpu/drm/meson/meson_venc.c

941

vic == 19 || /* 720p50 */

drivers/gpu/drm/meson/meson_venc.c

942

vic == 5 || /* 1080i60 */

drivers/gpu/drm/meson/meson_venc.c

943

vic == 20) /* 1080i50 */

drivers/gpu/drm/meson/meson_venc.c

950

void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,

drivers/gpu/drm/meson/meson_venc.c

992

if (meson_venc_hdmi_supported_vic(vic)) {

drivers/gpu/drm/meson/meson_venc.c

993

vmode = meson_venc_hdmi_get_vic_vmode(vic);

drivers/gpu/drm/meson/meson_venc.h

57

bool meson_venc_hdmi_supported_vic(int vic);

drivers/gpu/drm/meson/meson_venc.h

58

bool meson_venc_hdmi_venc_repeat(int vic);

drivers/gpu/drm/meson/meson_venc.h

66

void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,

drivers/gpu/drm/msm/dp/dp_ctrl.c

99

u32 vic;

drivers/gpu/drm/nouveau/include/nvkm/core/layout.h

53

NVKM_LAYOUT_ONCE(NVKM_ENGINE_VIC , struct nvkm_engine , vic)

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

373

unsigned int vic;

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

397

vic = ptr[3];

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

412

hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

559

char vic = cfg->infoframe.video_code;

drivers/gpu/drm/omapdrm/dss/hdmi5_core.c

562

range = vic > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED :

drivers/gpu/drm/rockchip/rk3066_hdmi.c

220

if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3)

drivers/gpu/drm/rockchip/rk3066_hdmi.c

29

int vic; /* The CEA Video ID (VIC) of the current drm display mode. */

drivers/gpu/drm/rockchip/rk3066_hdmi.c

338

hdmi->hdmi_data.vic = drm_match_cea_mode(mode);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

341

if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 ||

drivers/gpu/drm/rockchip/rk3066_hdmi.c

342

hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 ||

drivers/gpu/drm/rockchip/rk3066_hdmi.c

343

hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 ||

drivers/gpu/drm/rockchip/rk3066_hdmi.c

344

hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18)

drivers/gpu/drm/rockchip/rk3066_hdmi.c

489

u32 vic = drm_match_cea_mode(mode);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

491

if (vic > 1)

drivers/gpu/drm/stm/ltdc.c

1011

int vic = drm_match_cea_mode(mode);

drivers/gpu/drm/stm/ltdc.c

1014

if (vic == 6 || vic == 7 || vic == 21 || vic == 22 ||

drivers/gpu/drm/stm/ltdc.c

1015

vic == 2 || vic == 3 || vic == 17 || vic == 18)

drivers/gpu/drm/tegra/vic.c

101

falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,

drivers/gpu/drm/tegra/vic.c

104

&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,

drivers/gpu/drm/tegra/vic.c

105

(vic->falcon.firmware.iova + fce_bin_data_offset) >> 8);

drivers/gpu/drm/tegra/vic.c

108

err = falcon_wait_idle(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

110

dev_err(vic->dev,

drivers/gpu/drm/tegra/vic.c

123

struct vic *vic = to_vic(drm);

drivers/gpu/drm/tegra/vic.c

128

dev_err(vic->dev, "failed to attach to domain: %d\n", err);

drivers/gpu/drm/tegra/vic.c

132

vic->channel = host1x_channel_request(client);

drivers/gpu/drm/tegra/vic.c

133

if (!vic->channel) {

drivers/gpu/drm/tegra/vic.c

159

host1x_channel_put(vic->channel);

drivers/gpu/drm/tegra/vic.c

171

struct vic *vic = to_vic(drm);

drivers/gpu/drm/tegra/vic.c

185

host1x_channel_put(vic->channel);

drivers/gpu/drm/tegra/vic.c

188

vic->channel = NULL;

drivers/gpu/drm/tegra/vic.c

191

dma_unmap_single(vic->dev, vic->falcon.firmware.phys,

drivers/gpu/drm/tegra/vic.c

192

vic->falcon.firmware.size, DMA_TO_DEVICE);

drivers/gpu/drm/tegra/vic.c

193

tegra_drm_free(tegra, vic->falcon.firmware.size,

drivers/gpu/drm/tegra/vic.c

194

vic->falcon.firmware.virt,

drivers/gpu/drm/tegra/vic.c

195

vic->falcon.firmware.iova);

drivers/gpu/drm/tegra/vic.c

197

dma_free_coherent(vic->dev, vic->falcon.firmware.size,

drivers/gpu/drm/tegra/vic.c

198

vic->falcon.firmware.virt,

drivers/gpu/drm/tegra/vic.c

199

vic->falcon.firmware.iova);

drivers/gpu/drm/tegra/vic.c

210

static int vic_load_firmware(struct vic *vic)

drivers/gpu/drm/tegra/vic.c

212

struct host1x_client *client = &vic->client.base;

drivers/gpu/drm/tegra/vic.c

213

struct tegra_drm *tegra = vic->client.drm;

drivers/gpu/drm/tegra/vic.c

223

if (vic->falcon.firmware.virt) {

drivers/gpu/drm/tegra/vic.c

228

err = falcon_read_firmware(&vic->falcon, vic->config->firmware);

drivers/gpu/drm/tegra/vic.c

232

size = vic->falcon.firmware.size;

drivers/gpu/drm/tegra/vic.c

235

virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);

drivers/gpu/drm/tegra/vic.c

248

vic->falcon.firmware.virt = virt;

drivers/gpu/drm/tegra/vic.c

249

vic->falcon.firmware.iova = iova;

drivers/gpu/drm/tegra/vic.c

251

err = falcon_load_firmware(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

263

phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE);

drivers/gpu/drm/tegra/vic.c

265

err = dma_mapping_error(vic->dev, phys);

drivers/gpu/drm/tegra/vic.c

269

vic->falcon.firmware.phys = phys;

drivers/gpu/drm/tegra/vic.c

278

if (!vic->config->supports_sid) {

drivers/gpu/drm/tegra/vic.c

279

vic->can_use_context = false;

drivers/gpu/drm/tegra/vic.c

285

vic->can_use_context = false;

drivers/gpu/drm/tegra/vic.c

286

dev_warn_once(vic->dev, "context isolation disabled due to old firmware\n");

drivers/gpu/drm/tegra/vic.c

288

vic->can_use_context = true;

drivers/gpu/drm/tegra/vic.c

297

dma_free_coherent(vic->dev, size, virt, iova);

drivers/gpu/drm/tegra/vic.c

308

struct vic *vic = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/vic.c

311

err = clk_prepare_enable(vic->clk);

drivers/gpu/drm/tegra/vic.c

317

err = reset_control_deassert(vic->rst);

drivers/gpu/drm/tegra/vic.c

323

err = vic_load_firmware(vic);

drivers/gpu/drm/tegra/vic.c

327

err = vic_boot(vic);

drivers/gpu/drm/tegra/vic.c

334

reset_control_assert(vic->rst);

drivers/gpu/drm/tegra/vic.c

336

clk_disable_unprepare(vic->clk);

drivers/gpu/drm/tegra/vic.c

342

struct vic *vic = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/vic.c

345

host1x_channel_stop(vic->channel);

drivers/gpu/drm/tegra/vic.c

347

err = reset_control_assert(vic->rst);

drivers/gpu/drm/tegra/vic.c

353

clk_disable_unprepare(vic->clk);

drivers/gpu/drm/tegra/vic.c

361

struct vic *vic = to_vic(client);

drivers/gpu/drm/tegra/vic.c

363

context->channel = host1x_channel_get(vic->channel);

drivers/gpu/drm/tegra/vic.c

377

struct vic *vic = to_vic(client);

drivers/gpu/drm/tegra/vic.c

381

err = vic_load_firmware(vic);

drivers/gpu/drm/tegra/vic.c

385

*supported = vic->can_use_context;

drivers/gpu/drm/tegra/vic.c

45

static inline struct vic *to_vic(struct tegra_drm_client *client)

drivers/gpu/drm/tegra/vic.c

452

struct vic *vic;

drivers/gpu/drm/tegra/vic.c

462

vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);

drivers/gpu/drm/tegra/vic.c

463

if (!vic)

drivers/gpu/drm/tegra/vic.c

466

vic->config = of_device_get_match_data(dev);

drivers/gpu/drm/tegra/vic.c

47

return container_of(client, struct vic, client);

drivers/gpu/drm/tegra/vic.c

472

vic->regs = devm_platform_ioremap_resource(pdev, 0);

drivers/gpu/drm/tegra/vic.c

473

if (IS_ERR(vic->regs))

drivers/gpu/drm/tegra/vic.c

474

return PTR_ERR(vic->regs);

drivers/gpu/drm/tegra/vic.c

476

vic->clk = devm_clk_get(dev, NULL);

drivers/gpu/drm/tegra/vic.c

477

if (IS_ERR(vic->clk)) {

drivers/gpu/drm/tegra/vic.c

479

return PTR_ERR(vic->clk);

drivers/gpu/drm/tegra/vic.c

482

err = clk_set_rate(vic->clk, ULONG_MAX);

drivers/gpu/drm/tegra/vic.c

489

vic->rst = devm_reset_control_get(dev, "vic");

drivers/gpu/drm/tegra/vic.c

490

if (IS_ERR(vic->rst)) {

drivers/gpu/drm/tegra/vic.c

492

return PTR_ERR(vic->rst);

drivers/gpu/drm/tegra/vic.c

496

vic->falcon.dev = dev;

drivers/gpu/drm/tegra/vic.c

497

vic->falcon.regs = vic->regs;

drivers/gpu/drm/tegra/vic.c

499

err = falcon_init(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

50

static void vic_writel(struct vic *vic, u32 value, unsigned int offset)

drivers/gpu/drm/tegra/vic.c

503

platform_set_drvdata(pdev, vic);

drivers/gpu/drm/tegra/vic.c

505

INIT_LIST_HEAD(&vic->client.base.list);

drivers/gpu/drm/tegra/vic.c

506

vic->client.base.ops = &vic_client_ops;

drivers/gpu/drm/tegra/vic.c

507

vic->client.base.dev = dev;

drivers/gpu/drm/tegra/vic.c

508

vic->client.base.class = HOST1X_CLASS_VIC;

drivers/gpu/drm/tegra/vic.c

509

vic->client.base.syncpts = syncpts;

drivers/gpu/drm/tegra/vic.c

510

vic->client.base.num_syncpts = 1;

drivers/gpu/drm/tegra/vic.c

511

vic->dev = dev;

drivers/gpu/drm/tegra/vic.c

513

INIT_LIST_HEAD(&vic->client.list);

drivers/gpu/drm/tegra/vic.c

514

vic->client.version = vic->config->version;

drivers/gpu/drm/tegra/vic.c

515

vic->client.ops = &vic_ops;

drivers/gpu/drm/tegra/vic.c

517

err = host1x_client_register(&vic->client.base);

drivers/gpu/drm/tegra/vic.c

52

writel(value, vic->regs + offset);

drivers/gpu/drm/tegra/vic.c

530

falcon_exit(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

537

struct vic *vic = platform_get_drvdata(pdev);

drivers/gpu/drm/tegra/vic.c

540

host1x_client_unregister(&vic->client.base);

drivers/gpu/drm/tegra/vic.c

541

falcon_exit(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

55

static int vic_boot(struct vic *vic)

drivers/gpu/drm/tegra/vic.c

61

if (vic->config->supports_sid && tegra_dev_iommu_get_stream_id(vic->dev, &stream_id)) {

drivers/gpu/drm/tegra/vic.c

66

vic_writel(vic, value, VIC_TFBIF_TRANSCFG);

drivers/gpu/drm/tegra/vic.c

76

vic_writel(vic, stream_id, VIC_THI_STREAMID0);

drivers/gpu/drm/tegra/vic.c

79

vic_writel(vic, stream_id, VIC_THI_STREAMID1);

drivers/gpu/drm/tegra/vic.c

83

vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |

drivers/gpu/drm/tegra/vic.c

88

err = falcon_boot(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

92

hdr = vic->falcon.firmware.virt;

drivers/gpu/drm/tegra/vic.c

97

hdr = vic->falcon.firmware.virt +

drivers/gpu/drm/tests/drm_connector_test.c

1658

unsigned int vic = *(unsigned int *)test->param_value;

drivers/gpu/drm/tests/drm_connector_test.c

1660

mode = drm_kunit_display_mode_from_cea_vic(test, drm, vic);

drivers/gpu/drm/tests/drm_connector_test.c

1674

static void drm_hdmi_compute_mode_clock_yuv420_vic_desc(const unsigned int *vic, char *desc)

drivers/gpu/drm/tests/drm_connector_test.c

1676

sprintf(desc, "VIC %u", *vic);

drivers/gpu/drm/tests/drm_connector_test.c

1693

unsigned int vic =

drivers/gpu/drm/tests/drm_connector_test.c

1697

mode = drm_kunit_display_mode_from_cea_vic(test, drm, vic);

drivers/gpu/drm/tests/drm_connector_test.c

1718

unsigned int vic =

drivers/gpu/drm/tests/drm_connector_test.c

1722

mode = drm_kunit_display_mode_from_cea_vic(test, drm, vic);

drivers/irqchip/irq-aspeed-vic.c

103

generic_handle_domain_irq(vic->dom, irq);

drivers/irqchip/irq-aspeed-vic.c

109

struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-aspeed-vic.c

114

if (vic->edge_sources[sidx] & sbit)

drivers/irqchip/irq-aspeed-vic.c

115

writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);

drivers/irqchip/irq-aspeed-vic.c

120

struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-aspeed-vic.c

124

writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);

drivers/irqchip/irq-aspeed-vic.c

129

struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-aspeed-vic.c

133

writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);

drivers/irqchip/irq-aspeed-vic.c

139

struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-aspeed-vic.c

144

writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);

drivers/irqchip/irq-aspeed-vic.c

147

if (vic->edge_sources[sidx] & sbit)

drivers/irqchip/irq-aspeed-vic.c

148

writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);

drivers/irqchip/irq-aspeed-vic.c

162

struct aspeed_vic *vic = d->host_data;

drivers/irqchip/irq-aspeed-vic.c

170

if (vic->edge_sources[sidx] & sbit)

drivers/irqchip/irq-aspeed-vic.c

174

irq_set_chip_data(irq, vic);

drivers/irqchip/irq-aspeed-vic.c

188

struct aspeed_vic *vic;

drivers/irqchip/irq-aspeed-vic.c

199

vic = kzalloc_obj(struct aspeed_vic);

drivers/irqchip/irq-aspeed-vic.c

200

if (WARN_ON(!vic)) {

drivers/irqchip/irq-aspeed-vic.c

204

vic->base = regs;

drivers/irqchip/irq-aspeed-vic.c

207

vic_init_hw(vic);

drivers/irqchip/irq-aspeed-vic.c

210

system_avic = vic;

drivers/irqchip/irq-aspeed-vic.c

214

vic->dom = irq_domain_create_simple(of_fwnode_handle(node), NUM_IRQS, 0,

drivers/irqchip/irq-aspeed-vic.c

215

&avic_dom_ops, vic);

drivers/irqchip/irq-aspeed-vic.c

58

static void vic_init_hw(struct aspeed_vic *vic)

drivers/irqchip/irq-aspeed-vic.c

63

writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);

drivers/irqchip/irq-aspeed-vic.c

64

writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);

drivers/irqchip/irq-aspeed-vic.c

67

writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);

drivers/irqchip/irq-aspeed-vic.c

68

writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);

drivers/irqchip/irq-aspeed-vic.c

71

writel(0, vic->base + AVIC_INT_SELECT);

drivers/irqchip/irq-aspeed-vic.c

72

writel(0, vic->base + AVIC_INT_SELECT + 4);

drivers/irqchip/irq-aspeed-vic.c

78

sense = readl(vic->base + AVIC_INT_SENSE);

drivers/irqchip/irq-aspeed-vic.c

79

vic->edge_sources[0] = ~sense;

drivers/irqchip/irq-aspeed-vic.c

80

sense = readl(vic->base + AVIC_INT_SENSE + 4);

drivers/irqchip/irq-aspeed-vic.c

81

vic->edge_sources[1] = ~sense;

drivers/irqchip/irq-aspeed-vic.c

84

writel(0xffffffff, vic->base + AVIC_EDGE_CLR);

drivers/irqchip/irq-aspeed-vic.c

85

writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);

drivers/irqchip/irq-aspeed-vic.c

90

struct aspeed_vic *vic = system_avic;

drivers/irqchip/irq-aspeed-vic.c

95

stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);

drivers/irqchip/irq-aspeed-vic.c

97

stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);

drivers/irqchip/irq-vic.c

101

static void resume_one_vic(struct vic_device *vic)

drivers/irqchip/irq-vic.c

103

void __iomem *base = vic->base;

drivers/irqchip/irq-vic.c

110

writel(vic->int_select, base + VIC_INT_SELECT);

drivers/irqchip/irq-vic.c

111

writel(vic->protect, base + VIC_PROTECT);

drivers/irqchip/irq-vic.c

114

writel(vic->int_enable, base + VIC_INT_ENABLE);

drivers/irqchip/irq-vic.c

115

writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);

drivers/irqchip/irq-vic.c

119

writel(vic->soft_int, base + VIC_INT_SOFT);

drivers/irqchip/irq-vic.c

120

writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);

drivers/irqchip/irq-vic.c

131

static void suspend_one_vic(struct vic_device *vic)

drivers/irqchip/irq-vic.c

133

void __iomem *base = vic->base;

drivers/irqchip/irq-vic.c

137

vic->int_select = readl(base + VIC_INT_SELECT);

drivers/irqchip/irq-vic.c

138

vic->int_enable = readl(base + VIC_INT_ENABLE);

drivers/irqchip/irq-vic.c

139

vic->soft_int = readl(base + VIC_INT_SOFT);

drivers/irqchip/irq-vic.c

140

vic->protect = readl(base + VIC_PROTECT);

drivers/irqchip/irq-vic.c

145

writel(vic->resume_irqs, base + VIC_INT_ENABLE);

drivers/irqchip/irq-vic.c

146

writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);

drivers/irqchip/irq-vic.c

207

static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)

drivers/irqchip/irq-vic.c

212

while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {

drivers/irqchip/irq-vic.c

214

generic_handle_domain_irq(vic->domain, irq);

drivers/irqchip/irq-vic.c

225

struct vic_device *vic = irq_desc_get_handler_data(desc);

drivers/irqchip/irq-vic.c

229

while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {

drivers/irqchip/irq-vic.c

231

generic_handle_domain_irq(vic->domain, hwirq);

drivers/media/i2c/adv7604.c

1593

u8 vic = 0;

drivers/media/i2c/adv7604.c

1600

vic = infoframe_read(sd, 0x04);

drivers/media/i2c/adv7604.c

1602

if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&

drivers/media/v4l2-core/v4l2-dv-timings.c

239

bool v4l2_find_dv_timings_cea861_vic(struct v4l2_dv_timings *t, u8 vic)

drivers/media/v4l2-core/v4l2-dv-timings.c

248

bt->cea861_vic == vic) {

drivers/media/v4l2-core/v4l2-dv-timings.c

904

bool is_ce = avi->video_code || (hdmi && hdmi->vic);

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

415

unsigned vic;

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

439

vic = ptr[3];

drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c

454

hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);

drivers/video/hdmi.c

1503

if (hvf->vic == 0 && hvf->s3d_struct == HDMI_3D_STRUCTURE_INVALID) {

drivers/video/hdmi.c

1508

if (hvf->vic)

drivers/video/hdmi.c

1509

hdmi_log(" HDMI VIC: %u\n", hvf->vic);

drivers/video/hdmi.c

1776

hvf->vic = ptr[4];

drivers/video/hdmi.c

557

else if (frame->vic != 0 || frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID)

drivers/video/hdmi.c

571

if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID)

drivers/video/hdmi.c

644

} else if (frame->vic) {

drivers/video/hdmi.c

646

ptr[8] = frame->vic;

include/linux/hdmi.h

373

u8 vic;

include/media/v4l2-dv-timings.h

110

bool v4l2_find_dv_timings_cea861_vic(struct v4l2_dv_timings *t, u8 vic);