tw_writel
tw_writel(TW5864_INTR_CLR_L, 0xffff);
tw_writel(TW5864_INTR_CLR_H, 0xffff);
tw_writel(TW5864_VLC_STREAM_BASE_ADDR, cur_frame->vlc.dma_addr);
tw_writel(TW5864_MV_STREAM_BASE_ADDR, cur_frame->mv.dma_addr);
tw_writel(TW5864_VLC_DSP_INTR, 0x00000001);
tw_writel(TW5864_PCI_INTR_STATUS, TW5864_VLC_DONE_INTR);
tw_writel(TW5864_PCI_INTR_STATUS, TW5864_TIMER_INTR);
tw_writel(TW5864_INTR_ENABLE_L, dev->irqmask & 0xffff);
tw_writel(TW5864_INTR_ENABLE_H, (dev->irqmask >> 16));
tw_writel(TW5864_IND_DATA, data);
tw_writel(TW5864_IND_CTL, addr << 2 | TW5864_RW | TW5864_ENABLE);
tw_writel(TW5864_IND_CTL, addr << 2 | TW5864_ENABLE);
tw_writel(TW5864_FULL_HALF_MODE_SEL, 0);
tw_writel(TW5864_VLC_STREAM_BASE_ADDR,
tw_writel(TW5864_MV_STREAM_BASE_ADDR,
tw_writel(TW5864_SEN_EN_CH, 0x000f);
tw_writel(TW5864_H264EN_CH_EN, 0x000f);
tw_writel(TW5864_H264EN_BUS0_MAP, 0x00000000);
tw_writel(TW5864_H264EN_BUS1_MAP, 0x00001111);
tw_writel(TW5864_H264EN_BUS2_MAP, 0x00002222);
tw_writel(TW5864_H264EN_BUS3_MAP, 0x00003333);
tw_writel(TW5864_ENC_BUF_PTR_REC1, 0x00ff);
tw_writel(TW5864_PCI_INTTM_SCALE, 0);
tw_writel(TW5864_INTERLACING, TW5864_DI_EN);
tw_writel(TW5864_MASTER_ENB_REG, TW5864_PCI_VLC_INTR_ENB);
tw_writel(TW5864_PCI_INTR_CTL,
tw_writel(TW5864_VLC_RD, 0x1);
tw_writel((TW5864_VLC_STREAM_MEM_START + i * 4),
tw_writel(TW5864_VLC_RD, 0x0);
tw_writel((TW5864_QUAN_TAB + i * 4),
tw_writel((TW5864_QUAN_TAB + i * 4),
tw_writel(TW5864_DSP_PIC_MAX_MB,
tw_writel(TW5864_FRAME_WIDTH_BUS_A(nr),
tw_writel(TW5864_FRAME_WIDTH_BUS_B(nr),
tw_writel(TW5864_FRAME_HEIGHT_BUS_A(nr),
tw_writel(TW5864_FRAME_HEIGHT_BUS_B(nr),
tw_writel(TW5864_EMU, input->reg_emu);
tw_writel(TW5864_INTERLACING, input->reg_interlacing);
tw_writel(TW5864_DSP, input->reg_dsp);
tw_writel(TW5864_DSP_QP, input->reg_dsp_qp);
tw_writel(TW5864_DSP_REF_MVP_LAMBDA, input->reg_dsp_ref_mvp_lambda);
tw_writel(TW5864_DSP_I4x4_WEIGHT, input->reg_dsp_i4x4_weight);
tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN);
tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN |
tw_writel(TW5864_VLC,
tw_writel(TW5864_DSP_ENC_ORG_PTR_REG,
tw_writel(TW5864_DSP_ENC_REC,
tw_writel(TW5864_SLICE, TW5864_START_NSLICE);
tw_writel(TW5864_SLICE, 0);
tw_writel(TW5864_H264EN_RATE_CNTL_LO_WORD(input->nr, 0),
tw_writel(TW5864_H264EN_RATE_CNTL_HI_WORD(input->nr, 0),
tw_writel(reg->reg, reg->val);
tw_writel(reg, (tw_readl(reg) & ~(mask)) | ((value) & (mask)))
#define tw_setl(reg, bit) tw_writel((reg), tw_readl(reg) | (bit))
#define tw_clearl(reg, bit) tw_writel((reg), tw_readl(reg) & ~(bit))
tw_writel(TW68_VBIC, 0x03); /* 010 */
tw_writel(TW68_CAP_CTL, 0x03); /* 040 Enable both even & odd flds */
tw_writel(TW68_DMAC, 0x2000); /* patch set had 0x2080 */
tw_writel(TW68_TESTREG, 0); /* 02C */
tw_writel(TW68_GPIOC, 0); /* Set the GPIO to "normal", no ints */
tw_writel(TW68_GPOE, 0x0f); /* Set bits 0-3 to "output" */
tw_writel(TW68_GPDATA, 0); /* Set all bits to low state */
tw_writel(TW68_INTMASK, 0);
tw_writel(TW68_INTMASK, 0);
tw_writel(TW68_INTMASK, 0); /* 020 */
tw_writel(TW68_INTSTAT, 0xffffffff); /* 01C */
tw_writel(TW68_DMAC, 0x1600);
tw_writel(TW68_DMAP_SA, buf->dma);
tw_writel(TW68_INTSTAT, dev->board_virqmask);
tw_writel(reg->reg & 0xffff, reg->val);
tw_writel(TW68_INTSTAT, status);