tw_readl
status = tw_readl(TW5864_INTR_STATUS_L) |
tw_readl(TW5864_INTR_STATUS_H) << 16;
int channel = tw_readl(TW5864_DSP) & TW5864_DSP_ENC_CHN;
cur_frame->vlc_len = tw_readl(TW5864_VLC_LENGTH) << 2;
cur_frame->checksum = tw_readl(TW5864_VLC_CRC_REG);
tw_readl(TW5864_HW_VERSION));
tw_readl(TW5864_H264REV),
tw_readl(TW5864_UNDECLARED_H264REV_PART2));
while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries)
while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries)
return tw_readl(TW5864_IND_DATA);
while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries)
reg->val = tw_readl(reg->reg);
(tw_readl(reg) & (mask))
tw_writel(reg, (tw_readl(reg) & ~(mask)) | ((value) & (mask)))
#define tw_setl(reg, bit) tw_writel((reg), tw_readl(reg) | (bit))
#define tw_clearl(reg, bit) tw_writel((reg), tw_readl(reg) & ~(bit))
status = orig = tw_readl(TW68_INTSTAT) & dev->pci_irqmask;
status = tw_readl(TW68_INTSTAT) & dev->pci_irqmask;
dev->name, orig, tw_readl(TW68_INTSTAT));
reg = tw_readl(TW68_DMAC) & TW68_FIFO_EN;
cptr += sprintf(cptr, "%08x ", tw_readl(j));
cptr += sprintf(cptr, "%08x ", tw_readl(j));
reg->val = tw_readl(reg->reg);