upper_16_bits
#define PATCH_ID_CPUFEATURE_VALUE(p) upper_16_bits(p)
#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver) upper_16_bits(__ver)
upper_16_bits(val));
desc->xsizehi = upper_16_bits(len >> desc->tsz);
desc->xsizehi = upper_16_bits(len >> desc->tsz);
*secondary_addr = upper_16_bits(i2c_addr);
msg->msg_addr_high = upper_16_bits(addr);
.msg_addr_high = upper_16_bits(addr),
msg.msg_addr_high = upper_16_bits(addr);
msg.msg_addr_high = upper_16_bits(addr);
.msg_addr_high = upper_16_bits(addr)
return upper_16_bits(val);
upper_16_bits(pbus_address));
upper_16_bits(pbus_data));
upper_16_bits(pbus_address));
upper_16_bits(pbus_address));
upper_16_bits(pbus_address));
upper_16_bits(pbus_data_new));
upper_16_bits(address));
upper_16_bits(AEON_CPU_BOOT_ADDR));
PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));
PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));
upper_16_bits(start_sec));
upper_16_bits(start_nsec) & 0x3fff);
upper_16_bits(period_sec));
upper_16_bits(period_nsec) & 0x3fff);
upper_16_bits(sec));
upper_16_bits(nsec));
upper_16_bits(sec));
upper_16_bits(nsec));
phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
rate = LAN8841_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
: upper_16_bits(rate) & 0x3fff);
upper_16_bits(period_sec));
upper_16_bits(period_nsec) & 0x3fff);
upper_16_bits(start_sec));
upper_16_bits(start_nsec) & 0x3fff);
rate = MCHP_RDS_PTP_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
upper_16_bits(ts->tv_sec));
upper_16_bits(ts->tv_nsec) & GENMASK(13, 0));
#define QCOMTEE_ASYNC_VERSION_MAJOR(n) upper_16_bits(n)
#define RPMI_VER_MAJOR(__ver) upper_16_bits(__ver)
if (!ret && upper_16_bits(subid) == PCI_VENDOR_ID_ASUSTEK) {