ucc
for_each_node_by_name(ucc, "ucc")
par_io_of_config(ucc);
struct device_node *ucc;
struct udma_chan_config *ucc;
ucc = &uc->config;
ucc->remote_thread_id = filter_param->remote_thread_id;
ucc->atype = filter_param->atype;
ucc->asel = filter_param->asel;
ucc->tr_trigger_type = filter_param->tr_trigger_type;
if (ucc->tr_trigger_type) {
ucc->dir = DMA_MEM_TO_MEM;
} else if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET) {
ucc->dir = DMA_MEM_TO_DEV;
ucc->dir = DMA_DEV_TO_MEM;
ep_config = psil_get_ep_config(ucc->remote_thread_id);
ucc->remote_thread_id);
ucc->dir = DMA_MEM_TO_MEM;
ucc->remote_thread_id = -1;
ucc->atype = 0;
ucc->asel = 0;
ucc->remote_thread_id);
ucc->dir = DMA_MEM_TO_MEM;
ucc->remote_thread_id = -1;
ucc->atype = 0;
ucc->asel = 0;
ucc->pkt_mode = ep_config->pkt_mode;
ucc->channel_tpl = ep_config->channel_tpl;
ucc->notdpkt = ep_config->notdpkt;
ucc->ep_type = ep_config->ep_type;
ucc->mapped_channel_id = ep_config->mapped_channel_id;
ucc->default_flow_id = ep_config->default_flow_id;
ucc->mapped_channel_id = -1;
ucc->default_flow_id = -1;
if (ucc->ep_type != PSIL_EP_NATIVE) {
ucc->enable_acc32 = ep_config->pdma_acc32;
ucc->enable_burst = ep_config->pdma_burst;
ucc->needs_epib = ep_config->needs_epib;
ucc->psd_size = ep_config->psd_size;
ucc->metadata_size =
(ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) +
ucc->psd_size;
if (ucc->pkt_mode)
ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
ucc->metadata_size, ud->desc_align);
ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir));
ucc->tr_trigger_type);
struct udma_chan_config *ucc = &uc->config;
if (ucc->tr_trigger_type)
ucc->src_thread, ucc->dst_thread);
ucc->src_thread, ucc->dst_thread);
ucc->src_thread, ucc->dst_thread);
if (ucc->ep_type == PSIL_EP_NATIVE) {
if (ucc->metadata_size) {
seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : "");
if (ucc->psd_size)
seq_printf(s, " PSDsize:%u", ucc->psd_size);
if (ucc->enable_acc32 || ucc->enable_burst)
ucc->enable_acc32 ? " ACC32" : "",
ucc->enable_burst ? " BURST" : "");
seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode");
struct udma_chan_config *ucc = &uc->config;
if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode &&
(uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) {
struct ucc ucc1; /* ucc1 */
struct ucc ucc3; /* ucc3 */
struct ucc ucc5; /* ucc5 */
struct ucc ucc7; /* ucc7 */
struct ucc ucc2; /* ucc2 */
struct ucc ucc4; /* ucc4 */
struct ucc ucc6; /* ucc6 */
struct ucc ucc8; /* ucc8 */