arch/loongarch/include/asm/hw_breakpoint.h

47

#define CSR_CFG_CTRL (CSR_CFG_MASK + LOONGARCH_MAX_BRP)

arch/loongarch/kernel/hw_breakpoint.c

224

write_wb_reg(CSR_CFG_MASK, i, 0, info->mask);

arch/loongarch/kernel/hw_breakpoint.c

229

write_wb_reg(CSR_CFG_MASK, i, 1, info->mask);

arch/loongarch/kernel/hw_breakpoint.c

243

write_wb_reg(CSR_CFG_MASK, i, 0, 0);

arch/loongarch/kernel/hw_breakpoint.c

248

write_wb_reg(CSR_CFG_MASK, i, 1, 0);

arch/loongarch/kernel/hw_breakpoint.c

552

mask = read_wb_reg(CSR_CFG_MASK, 0, 0);

arch/loongarch/kernel/hw_breakpoint.c

84

GEN_READ_WB_REG_CASES(CSR_CFG_MASK, MASK, t, val);

arch/loongarch/kernel/hw_breakpoint.c

99

GEN_WRITE_WB_REG_CASES(CSR_CFG_MASK, MASK, t, val);