drivers/clocksource/renesas-ostm.c

114

writel(timer_of_period(to) - 1, timer_of_base(to) + OSTM_CMP);

drivers/clocksource/renesas-ostm.c

115

writeb(CTL_PERIODIC, timer_of_base(to) + OSTM_CTL);

drivers/clocksource/renesas-ostm.c

116

writeb(TS, timer_of_base(to) + OSTM_TS);

drivers/clocksource/renesas-ostm.c

48

if (readb(timer_of_base(to) + OSTM_TE) & TE) {

drivers/clocksource/renesas-ostm.c

49

writeb(TT, timer_of_base(to) + OSTM_TT);

drivers/clocksource/renesas-ostm.c

56

while (readb(timer_of_base(to) + OSTM_TE) & TE)

drivers/clocksource/renesas-ostm.c

65

writel(0, timer_of_base(to) + OSTM_CMP);

drivers/clocksource/renesas-ostm.c

66

writeb(CTL_FREERUN, timer_of_base(to) + OSTM_CTL);

drivers/clocksource/renesas-ostm.c

67

writeb(TS, timer_of_base(to) + OSTM_TS);

drivers/clocksource/renesas-ostm.c

69

return clocksource_mmio_init(timer_of_base(to) + OSTM_CNT,

drivers/clocksource/renesas-ostm.c

81

system_clock = timer_of_base(to) + OSTM_CNT;

drivers/clocksource/renesas-ostm.c

92

writel(delta, timer_of_base(to) + OSTM_CMP);

drivers/clocksource/renesas-ostm.c

93

writeb(CTL_ONESHOT, timer_of_base(to) + OSTM_CTL);

drivers/clocksource/renesas-ostm.c

94

writeb(TS, timer_of_base(to) + OSTM_TS);

drivers/clocksource/timer-gx6605s.c

151

gx6605s_clkevt_init(timer_of_base(&to));

drivers/clocksource/timer-gx6605s.c

153

return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET);

drivers/clocksource/timer-gx6605s.c

28

void __iomem *base = timer_of_base(to_timer_of(ce));

drivers/clocksource/timer-gx6605s.c

40

void __iomem *base = timer_of_base(to_timer_of(ce));

drivers/clocksource/timer-gx6605s.c

55

void __iomem *base = timer_of_base(to_timer_of(ce));

drivers/clocksource/timer-gx6605s.c

69

void __iomem *base = timer_of_base(to_timer_of(ce));

drivers/clocksource/timer-gx6605s.c

98

base = timer_of_base(&to) + CLKSRC_OFFSET;

drivers/clocksource/timer-imx-sysctr.c

160

base = timer_of_base(&to_sysctr);

drivers/clocksource/timer-imx-sysctr.c

37

void __iomem *base = timer_of_base(to);

drivers/clocksource/timer-imx-sysctr.c

56

void __iomem *base = timer_of_base(to);

drivers/clocksource/timer-imx-sysctr.c

72

void __iomem *base = timer_of_base(to);

drivers/clocksource/timer-imx-tpm.c

205

timer_base = timer_of_base(&to_tpm);

drivers/clocksource/timer-loongson1-pwm.c

228

ls1x_clocksource.reg_base = timer_of_base(to);

drivers/clocksource/timer-loongson1-pwm.c

47

writel(period, timer_of_base(to) + PWM_LRC);

drivers/clocksource/timer-loongson1-pwm.c

48

writel(period, timer_of_base(to) + PWM_HRC);

drivers/clocksource/timer-loongson1-pwm.c

53

writel(0, timer_of_base(to) + PWM_CNTR);

drivers/clocksource/timer-loongson1-pwm.c

58

writel((INT_EN | PWM_OE | CNT_EN), timer_of_base(to) + PWM_CTRL);

drivers/clocksource/timer-loongson1-pwm.c

63

writel(0, timer_of_base(to) + PWM_CTRL);

drivers/clocksource/timer-loongson1-pwm.c

70

val = readl(timer_of_base(to) + PWM_CTRL);

drivers/clocksource/timer-loongson1-pwm.c

72

writel(val, timer_of_base(to) + PWM_CTRL);

drivers/clocksource/timer-mediatek-cpux.c

39

writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);

drivers/clocksource/timer-mediatek-cpux.c

40

return readl(timer_of_base(to) + CPUX_CON_REG);

drivers/clocksource/timer-mediatek-cpux.c

45

writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);

drivers/clocksource/timer-mediatek-cpux.c

46

writel(val, timer_of_base(to) + CPUX_CON_REG);

drivers/clocksource/timer-mediatek.c

143

val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));

drivers/clocksource/timer-mediatek.c

144

writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +

drivers/clocksource/timer-mediatek.c

151

writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));

drivers/clocksource/timer-mediatek.c

160

writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);

drivers/clocksource/timer-mediatek.c

162

val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));

drivers/clocksource/timer-mediatek.c

173

timer_of_base(to) + GPT_CTRL_REG(timer));

drivers/clocksource/timer-mediatek.c

212

writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);

drivers/clocksource/timer-mediatek.c

222

timer_of_base(to) + GPT_CTRL_REG(timer));

drivers/clocksource/timer-mediatek.c

225

timer_of_base(to) + GPT_CLK_REG(timer));

drivers/clocksource/timer-mediatek.c

227

writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));

drivers/clocksource/timer-mediatek.c

230

timer_of_base(to) + GPT_CTRL_REG(timer));

drivers/clocksource/timer-mediatek.c

238

writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);

drivers/clocksource/timer-mediatek.c

241

writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);

drivers/clocksource/timer-mediatek.c

243

val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);

drivers/clocksource/timer-mediatek.c

245

timer_of_base(to) + GPT_IRQ_EN_REG);

drivers/clocksource/timer-mediatek.c

260

writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);

drivers/clocksource/timer-mediatek.c

267

writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);

drivers/clocksource/timer-mediatek.c

325

clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),

drivers/clocksource/timer-mediatek.c

328

gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);

drivers/clocksource/timer-mediatek.c

56

#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)

drivers/clocksource/timer-mediatek.c

57

#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)

drivers/clocksource/timer-milbeaut.c

129

writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);

drivers/clocksource/timer-milbeaut.c

130

writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);

drivers/clocksource/timer-milbeaut.c

131

writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);

drivers/clocksource/timer-milbeaut.c

133

writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);

drivers/clocksource/timer-milbeaut.c

139

writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);

drivers/clocksource/timer-milbeaut.c

165

return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS);

drivers/clocksource/timer-milbeaut.c

179

clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS,

drivers/clocksource/timer-milbeaut.c

55

val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);

drivers/clocksource/timer-milbeaut.c

57

writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);

drivers/clocksource/timer-milbeaut.c

71

writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);

drivers/clocksource/timer-milbeaut.c

76

u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);

drivers/clocksource/timer-milbeaut.c

79

writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);

drivers/clocksource/timer-milbeaut.c

84

writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);

drivers/clocksource/timer-msc313e.c

104

msc313e_timer_stop(timer_of_base(timer));

drivers/clocksource/timer-msc313e.c

105

msc313e_timer_start(timer_of_base(timer), false);

drivers/clocksource/timer-msc313e.c

114

msc313e_timer_stop(timer_of_base(timer));

drivers/clocksource/timer-msc313e.c

115

msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer));

drivers/clocksource/timer-msc313e.c

116

msc313e_timer_start(timer_of_base(timer), true);

drivers/clocksource/timer-msc313e.c

125

msc313e_timer_stop(timer_of_base(timer));

drivers/clocksource/timer-msc313e.c

126

msc313e_timer_setup(timer_of_base(timer), evt);

drivers/clocksource/timer-msc313e.c

127

msc313e_timer_start(timer_of_base(timer), false);

drivers/clocksource/timer-msc313e.c

187

writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE);

drivers/clocksource/timer-msc313e.c

210

msc313e_clksrc = timer_of_base(&to);

drivers/clocksource/timer-msc313e.c

216

msc313e_delay.base = timer_of_base(&to);

drivers/clocksource/timer-msc313e.c

224

return clocksource_mmio_init(timer_of_base(&to), TIMER_NAME, timer_of_rate(&to), 300, 32,

drivers/clocksource/timer-msc313e.c

95

msc313e_timer_stop(timer_of_base(timer));

drivers/clocksource/timer-npcm7xx.c

100

val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

103

writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

114

writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0);

drivers/clocksource/timer-npcm7xx.c

115

val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

117

writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

127

writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR);

drivers/clocksource/timer-npcm7xx.c

158

timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

161

timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR);

drivers/clocksource/timer-npcm7xx.c

174

timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);

drivers/clocksource/timer-npcm7xx.c

176

timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TICR1);

drivers/clocksource/timer-npcm7xx.c

178

val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);

drivers/clocksource/timer-npcm7xx.c

180

writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);

drivers/clocksource/timer-npcm7xx.c

182

clocksource_mmio_init(timer_of_base(&npcm7xx_to) +

drivers/clocksource/timer-npcm7xx.c

216

timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to));

drivers/clocksource/timer-npcm7xx.c

61

val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

63

writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

73

val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

75

writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

85

val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

88

writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

drivers/clocksource/timer-npcm7xx.c

98

writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);

drivers/clocksource/timer-rda.c

110

rda_ostimer_start(timer_of_base(to), false, evt);

drivers/clocksource/timer-rda.c

122

timer_of_base(to) + RDA_TIMER_IRQ_CLR);

drivers/clocksource/timer-rda.c

159

void __iomem *base = timer_of_base(&rda_ostimer_of);

drivers/clocksource/timer-rda.c

72

rda_ostimer_stop(timer_of_base(to));

drivers/clocksource/timer-rda.c

81

rda_ostimer_stop(timer_of_base(to));

drivers/clocksource/timer-rda.c

91

rda_ostimer_stop(timer_of_base(to));

drivers/clocksource/timer-rda.c

95

rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy);

drivers/clocksource/timer-realtek.c

143

systimer_base = timer_of_base(&rtk_timer_to);

drivers/clocksource/timer-sprd.c

107

sprd_timer_disable(timer_of_base(to));

drivers/clocksource/timer-sprd.c

116

sprd_timer_clear_interrupt(timer_of_base(to));

drivers/clocksource/timer-sprd.c

119

sprd_timer_disable(timer_of_base(to));

drivers/clocksource/timer-sprd.c

153

sprd_timer_enable_interrupt(timer_of_base(&to));

drivers/clocksource/timer-sprd.c

169

hi = readl_relaxed(timer_of_base(&suspend_to) +

drivers/clocksource/timer-sprd.c

171

lo = readl_relaxed(timer_of_base(&suspend_to) +

drivers/clocksource/timer-sprd.c

173

} while (hi != readl_relaxed(timer_of_base(&suspend_to) + TIMER_VALUE_SHDW_HI));

drivers/clocksource/timer-sprd.c

181

timer_of_base(&suspend_to) + TIMER_LOAD_LO);

drivers/clocksource/timer-sprd.c

183

timer_of_base(&suspend_to) + TIMER_LOAD_HI);

drivers/clocksource/timer-sprd.c

184

sprd_timer_enable(timer_of_base(&suspend_to),

drivers/clocksource/timer-sprd.c

192

sprd_timer_disable(timer_of_base(&suspend_to));

drivers/clocksource/timer-sprd.c

85

sprd_timer_disable(timer_of_base(to));

drivers/clocksource/timer-sprd.c

86

sprd_timer_update_counter(timer_of_base(to), cycles);

drivers/clocksource/timer-sprd.c

87

sprd_timer_enable(timer_of_base(to), 0);

drivers/clocksource/timer-sprd.c

96

sprd_timer_disable(timer_of_base(to));

drivers/clocksource/timer-sprd.c

97

sprd_timer_update_counter(timer_of_base(to), timer_of_period(to));

drivers/clocksource/timer-sprd.c

98

sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE);

drivers/clocksource/timer-stm32.c

101

writel_relaxed(0, timer_of_base(to) + TIM_DIER);

drivers/clocksource/timer-stm32.c

114

writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);

drivers/clocksource/timer-stm32.c

132

next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt;

drivers/clocksource/timer-stm32.c

133

writel_relaxed(next, timer_of_base(to) + TIM_CCR1);

drivers/clocksource/timer-stm32.c

134

now = readl_relaxed(timer_of_base(to) + TIM_CNT);

drivers/clocksource/timer-stm32.c

139

writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER);

drivers/clocksource/timer-stm32.c

167

writel_relaxed(0, timer_of_base(to) + TIM_SR);

drivers/clocksource/timer-stm32.c

192

writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR);

drivers/clocksource/timer-stm32.c

194

width = readl_relaxed(timer_of_base(to) + TIM_ARR);

drivers/clocksource/timer-stm32.c

222

writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);

drivers/clocksource/timer-stm32.c

223

writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);

drivers/clocksource/timer-stm32.c

224

writel_relaxed(0, timer_of_base(to) + TIM_SR);

drivers/clocksource/timer-stm32.c

253

stm32_timer_cnt = timer_of_base(to) + TIM_CNT;

drivers/clocksource/timer-stm32.c

263

return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name,

drivers/clocksource/timer-sun4i.c

106

sun4i_clkevt_time_stop(timer_of_base(to), 0);

drivers/clocksource/timer-sun4i.c

107

sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));

drivers/clocksource/timer-sun4i.c

108

sun4i_clkevt_time_start(timer_of_base(to), 0, true);

drivers/clocksource/timer-sun4i.c

118

sun4i_clkevt_time_stop(timer_of_base(to), 0);

drivers/clocksource/timer-sun4i.c

119

sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);

drivers/clocksource/timer-sun4i.c

120

sun4i_clkevt_time_start(timer_of_base(to), 0, false);

drivers/clocksource/timer-sun4i.c

135

sun4i_timer_clear_interrupt(timer_of_base(to));

drivers/clocksource/timer-sun4i.c

165

return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));

drivers/clocksource/timer-sun4i.c

177

writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));

drivers/clocksource/timer-sun4i.c

180

timer_of_base(&to) + TIMER_CTL_REG(1));

drivers/clocksource/timer-sun4i.c

193

ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),

drivers/clocksource/timer-sun4i.c

202

timer_of_base(&to) + TIMER_CTL_REG(0));

drivers/clocksource/timer-sun4i.c

205

sun4i_clkevt_time_stop(timer_of_base(&to), 0);

drivers/clocksource/timer-sun4i.c

208

sun4i_timer_clear_interrupt(timer_of_base(&to));

drivers/clocksource/timer-sun4i.c

214

val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);

drivers/clocksource/timer-sun4i.c

215

writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);

drivers/clocksource/timer-sun4i.c

87

sun4i_clkevt_time_stop(timer_of_base(to), 0);

drivers/clocksource/timer-sun4i.c

96

sun4i_clkevt_time_stop(timer_of_base(to), 0);

drivers/clocksource/timer-sun4i.c

97

sun4i_clkevt_time_start(timer_of_base(to), 0, false);

drivers/clocksource/timer-tegra.c

106

void __iomem *reg_base = timer_of_base(to_timer_of(evt));

drivers/clocksource/timer-tegra.c

136

writel_relaxed(0, timer_of_base(to) + TIMER_PTV);

drivers/clocksource/timer-tegra.c

137

writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);

drivers/clocksource/timer-tegra.c

195

void __iomem *reg_base = timer_of_base(&suspend_rtc_to);

drivers/clocksource/timer-tegra.c

261

timer_reg_base = timer_of_base(to);

drivers/clocksource/timer-tegra.c

57

void __iomem *reg_base = timer_of_base(to_timer_of(evt));

drivers/clocksource/timer-tegra.c

75

void __iomem *reg_base = timer_of_base(to_timer_of(evt));

drivers/clocksource/timer-tegra.c

84

void __iomem *reg_base = timer_of_base(to_timer_of(evt));

drivers/clocksource/timer-tegra.c

96

void __iomem *reg_base = timer_of_base(to_timer_of(evt));