drivers/gpu/drm/i915/display/intel_ddi.c

1289

enum tc_port tc_port = intel_encoder_to_tc(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1301

intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1303

intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1313

intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1319

intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1330

intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1339

intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1355

intel_de_rmw(display, MG_CLKHUB(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1362

intel_de_rmw(display, MG_TX1_DCC(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1369

intel_de_rmw(display, MG_TX2_DCC(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1379

intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1381

intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1390

enum tc_port tc_port = intel_encoder_to_tc(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1410

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1413

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1418

intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1422

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1432

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1440

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1459

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1848

enum tc_port tc_port = intel_encoder_to_tc(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1860

ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1868

enum tc_port tc_port = intel_encoder_to_tc(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1874

0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));

drivers/gpu/drm/i915/display/intel_ddi.c

1884

enum tc_port tc_port = intel_encoder_to_tc(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1895

return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));

drivers/gpu/drm/i915/display/intel_ddi.c

1901

enum tc_port tc_port = intel_encoder_to_tc(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1916

id = icl_tc_port_to_pll_id(tc_port);

drivers/gpu/drm/i915/display/intel_ddi.c

2164

enum tc_port tc_port, u32 ln0, u32 ln1)

drivers/gpu/drm/i915/display/intel_ddi.c

2166

if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))

drivers/gpu/drm/i915/display/intel_ddi.c

2167

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);

drivers/gpu/drm/i915/display/intel_ddi.c

2168

if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))

drivers/gpu/drm/i915/display/intel_ddi.c

2169

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);

drivers/gpu/drm/i915/display/intel_ddi.c

2177

enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);

drivers/gpu/drm/i915/display/intel_ddi.c

2190

ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));

drivers/gpu/drm/i915/display/intel_ddi.c

2191

ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));

drivers/gpu/drm/i915/display/intel_ddi.c

2193

ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));

drivers/gpu/drm/i915/display/intel_ddi.c

2194

ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));

drivers/gpu/drm/i915/display/intel_ddi.c

2252

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);

drivers/gpu/drm/i915/display/intel_ddi.c

2253

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);

drivers/gpu/drm/i915/display/intel_ddi.c

2256

tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);

drivers/gpu/drm/i915/display/intel_ddi.c

2259

intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);

drivers/gpu/drm/i915/display/intel_ddi.c

2260

intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);

drivers/gpu/drm/i915/display/intel_ddi.c

3723

enum tc_port tc_port = intel_encoder_to_tc(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3727

intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

5094

#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')

drivers/gpu/drm/i915/display/intel_ddi.c

5153

enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5158

tc_port != TC_PORT_NONE ? "TC" : "",

drivers/gpu/drm/i915/display/intel_ddi.c

5159

tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));

drivers/gpu/drm/i915/display/intel_ddi.c

5161

enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5166

tc_port != TC_PORT_NONE ? "TC" : "",

drivers/gpu/drm/i915/display/intel_ddi.c

5167

tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));

drivers/gpu/drm/i915/display/intel_display.c

1896

enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display.c

1909

enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display.c

1949

enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder)

drivers/gpu/drm/i915/display/intel_display.h

409

enum tc_port intel_port_to_tc(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display.h

410

enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display.h

416

enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);

drivers/gpu/drm/i915/display/intel_display_power_well.c

618

enum tc_port tc_port;

drivers/gpu/drm/i915/display/intel_display_power_well.c

620

tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);

drivers/gpu/drm/i915/display/intel_display_power_well.c

622

ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)),

drivers/gpu/drm/i915/display/intel_display_regs.h

2869

#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \

drivers/gpu/drm/i915/display/intel_display_regs.h

2870

(tc_port) + 12 : \

drivers/gpu/drm/i915/display/intel_display_regs.h

2871

(tc_port) - TC_PORT_4 + 21))

drivers/gpu/drm/i915/display/intel_display_regs.h

2946

#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \

drivers/gpu/drm/i915/display/intel_display_regs.h

2957

#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_dkl_phy.c

26

enum tc_port tc_port = DKL_REG_TC_PORT(reg);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

29

tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS))

drivers/gpu/drm/i915/display/intel_dkl_phy.c

33

HIP_INDEX_REG(tc_port),

drivers/gpu/drm/i915/display/intel_dkl_phy.c

34

HIP_INDEX_VAL(tc_port, reg.bank_idx));

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

105

#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

113

#define DKL_REFCLKIN_CTL(tc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

118

#define DKL_CLKTOP2_HSCLKCTL(rc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

123

#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

129

#define DKL_TX_DPCNTL0(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

141

#define DKL_TX_DPCNTL1(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

148

#define DKL_TX_DPCNTL2(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

160

#define DKL_TX_FW_CALIB(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

167

#define DKL_TX_PMD_LANE_SUS(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

173

#define DKL_TX_DW17(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

179

#define DKL_TX_DW18(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

185

#define DKL_DP_MODE(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

190

#define DKL_CMN_UC_DW_27(tc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

202

#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

204

#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4))

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

205

#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

31

#define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

41

#define _DKL_REG(tc_port, phy_offset) \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

43

.reg = _DKL_REG_PHY_BASE(tc_port) + \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

48

#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

49

_DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

53

#define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

59

#define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

78

#define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

86

#define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

97

#define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

197

static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

202

enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

204

return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

241

enum tc_port tc_port = icl_pll_id_to_tc_port(id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

244

return ADLP_PORTTC_PLL_ENABLE(tc_port);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

246

return MG_PLL_ENABLE(tc_port);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3601

enum tc_port tc_port = icl_pll_id_to_tc_port(id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3618

MG_REFCLKIN_CTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3622

intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3627

intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3634

hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3635

hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3636

hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3638

MG_PLL_FRAC_LOCK(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3639

hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3641

hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3643

intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3668

enum tc_port tc_port = icl_pll_id_to_tc_port(id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3687

DKL_REFCLKIN_CTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3691

intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3699

intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3703

hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3709

hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3713

hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3719

hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3724

intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3857

enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3865

intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3868

intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3872

intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3879

intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3880

intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3881

intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3882

intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3884

intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3886

intel_de_rmw(display, MG_PLL_BIAS(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3889

intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3893

intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3900

enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3908

val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3911

intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3913

val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3916

intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3918

val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3924

intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3929

intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3932

val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3936

intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3938

val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3944

intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3946

val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3950

intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3952

val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3956

intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3958

intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

36

enum tc_port;

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

450

enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

105

#define MG_CLKHUB(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

106

MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

11

#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

115

#define MG_TX1_DCC(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

116

MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

12

_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

123

#define MG_TX2_DCC(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

124

MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

135

#define MG_DP_MODE(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

136

MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

163

#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

173

#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

18

#define MG_TX1_LINK_PARAMS(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

19

MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

191

#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

203

#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

216

#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

227

#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

238

#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

250

#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

268

#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

27

#define MG_TX2_LINK_PARAMS(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

278

#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

28

MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

37

#define MG_TX1_PISO_READLOAD(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

38

MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

46

#define MG_TX2_PISO_READLOAD(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

47

MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

56

#define MG_TX1_SWINGCTRL(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

57

MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

65

#define MG_TX2_SWINGCTRL(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

66

MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

80

#define MG_TX1_DRVCTRL(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

81

MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

89

#define MG_TX2_DRVCTRL(ln, tc_port) \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

90

MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \

drivers/gpu/drm/i915/display/intel_tc.c

1974

enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);

drivers/gpu/drm/i915/display/intel_tc.c

1976

if (drm_WARN_ON(display->drm, tc_port == TC_PORT_NONE))

drivers/gpu/drm/i915/display/intel_tc.c

1996

tc_port + 1);

drivers/gpu/drm/i915/display/intel_tc.c

251

enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);

drivers/gpu/drm/i915/display/intel_tc.c

253

if (tc_port == TC_PORT_NONE)

drivers/gpu/drm/i915/display/intel_tc.c

256

return POWER_DOMAIN_PORT_DDI_LANES_TC1 + tc_port - TC_PORT_1;

drivers/gpu/drm/i915/display/intel_tc.c

295

enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);

drivers/gpu/drm/i915/display/intel_tc.c

305

reg = TCSS_DDI_STATUS(tc_port);

drivers/gpu/drm/i915/display/intel_tc.c

491

enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);

drivers/gpu/drm/i915/display/intel_tc.c

498

tc->phy_fia = tc_port / 2;

drivers/gpu/drm/i915/display/intel_tc.c

499

tc->phy_fia_idx = tc_port % 2;

drivers/gpu/drm/i915/display/intel_tc.c

502

tc->phy_fia_idx = tc_port;

drivers/gpu/drm/i915/display/intel_tc.c

847

enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);

drivers/gpu/drm/i915/display/intel_tc.c

852

val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));

drivers/platform/chrome/cros_ec_typec.c

114

typec_set_data_role(tc_port, target_role);

drivers/platform/chrome/cros_ec_typec.c

122

typec_set_pwr_role(tc_port, target_role);

drivers/platform/chrome/cros_ec_typec.c

47

static int cros_typec_enter_usb_mode(struct typec_port *tc_port, enum usb_mode mode)

drivers/platform/chrome/cros_ec_typec.c

49

struct cros_typec_port *port = typec_get_drvdata(tc_port);

drivers/platform/chrome/cros_ec_typec.c

61

static int cros_typec_perform_role_swap(struct typec_port *tc_port, int target_role, u8 swap_type)

drivers/platform/chrome/cros_ec_typec.c

63

struct cros_typec_port *port = typec_get_drvdata(tc_port);