drivers/gpu/drm/tilcdc/tilcdc_crtc.c

290

reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

326

reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

373

reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

734

if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

968

reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);

drivers/gpu/drm/tilcdc/tilcdc_drv.c

243

switch (tilcdc_read(ddev, LCDC_PID_REG)) {

drivers/gpu/drm/tilcdc/tilcdc_drv.c

254

tilcdc_read(ddev, LCDC_PID_REG));

drivers/gpu/drm/tilcdc/tilcdc_drv.c

454

tilcdc_read(dev, registers[i].reg));

drivers/gpu/drm/tilcdc/tilcdc_regs.h

143

tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask));

drivers/gpu/drm/tilcdc/tilcdc_regs.h

148

tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);

drivers/gpu/drm/tilcdc/tilcdc_regs.h

153

tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);

drivers/gpu/drm/tilcdc/tilcdc_regs.h

165

return tilcdc_read(dev, tilcdc_irqstatus_reg(dev));