CSR
l = dma_read(CSR, lch);
[CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
p->dma_read(CSR, lch);
csr = p->dma_read(CSR, ch);
p->dma_read(CSR, lch);
[CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
omap_dma_chan_read(c, CSR);
omap_dma_chan_write(c, CSR, ~0);
unsigned val = omap_dma_chan_read(c, CSR);
omap_dma_chan_write(c, CSR, val);
BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
channel64_readl(dc, CSR));
channel32_readl(dc, CSR));
if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
channel64_writel(dc, CSR, 0xffffffff);
channel32_writel(dc, CSR, 0xffffffff);
desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
d->SAIR, d->DAIR, d->CCR, d->CSR);
channel_writel(dc, CSR, errors);
csr = channel64_readl(dc, CSR);
channel64_writel(dc, CSR, csr);
csr = channel32_readl(dc, CSR);
channel32_writel(dc, CSR, csr);
csr = channel_readl(dc, CSR);
channel_readl(dc, CSR));
csr = channel_readl(dc, CSR);
if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
TXX9_DMA_REG32(CSR); /* Channel Status Register */
u32 CSR;
case CSR:
switch (tnt_readb(tnt_priv, CSR) & 0xf0) {
_q->qcr = RISCV_IOMMU_REG_ ## name ## CSR; \
error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
error = ravb_wait(ndev, CSR, CSR_RPO, 0);
error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops);
BCM59056_SR_DESC(CSR, csr, dcdc_csr_ranges),
BCM59054_SR_DESC(CSR, csr, dcdc_csr_ranges),
BCM59054_SR_DESC(CSR, csr, dcdc_csr_ranges),
#define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
#define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
#define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
#define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
#define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
#define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
#define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
#define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
#define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
#define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
#define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
#define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
#define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
#define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
#define src_writeb(AEP, CSR, value) writeb(value, \
&((AEP)->regs.src.bar0->CSR))
#define src_writel(AEP, CSR, value) writel(value, \
&((AEP)->regs.src.bar0->CSR))
#define src_writeq(AEP, CSR, value) writeq(value, \
&((AEP)->regs.src.bar0->CSR))
aus->status = at91_usart_spi_readl(aus, CSR);
unsigned int status = rsci_serial_in(port, CSR);
status = rsci_serial_in(port, CSR);
status = rsci_serial_in(port, CSR);
rsci_serial_in(port, CSR); /* dummy read */
rsci_serial_in(port, CSR); /* dummy read */
ret = readl_relaxed_poll_timeout_atomic(port->membase + CSR, status,
.status = CSR,
.overrun_reg = CSR,
.overrun_reg = CSR,